Henrik Rydgård
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c41f875df4
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Remove base/logging.h in a whole lot more places.
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2020-08-15 19:09:00 +02:00 |
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Henrik Rydgård
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6f1915110f
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Remove base/logging from UI and more
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2020-08-15 19:08:54 +02:00 |
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Henrik Rydgård
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b43698a13d
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Remove most instances of base/logging.h from Common, Core, GPU, more
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2020-08-15 19:08:44 +02:00 |
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Unknown W. Brackets
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4b4e3432cd
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SaveState: Split Do() into a separate header.
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2020-08-10 08:03:41 +00:00 |
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Henrik Rydgård
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c5e0b799d9
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Remove category from _assert_msg_ functions. We don't filter these by category anyway.
Fixes the inconsistency where we _assert_ didn't take a category but
_assert_msg_ did.
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2020-07-19 20:33:25 +02:00 |
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Henrik Rydgård
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6f97c3d422
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Various platform buildfixes
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2020-07-14 09:25:59 +02:00 |
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Henrik Rydgard
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c988d42b04
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ARM/ARM64 instruction analysis, hook up to handler
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2020-07-14 09:25:45 +02:00 |
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Unknown W. Brackets
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ae224b3893
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jit: Add some basic checks in armjit/arm64jit.
Just the simple (and unlikely) case so far...
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2020-07-13 01:49:19 -07:00 |
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Unknown W. Brackets
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7910b4029a
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arm64jit: Track writable and non-writable pointers.
Switch uses different memory regions. We can handle this, might as well
cleanup some const abuse.
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2020-05-17 00:15:12 -07:00 |
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Henrik Rydgård
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f65a71d6d8
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Compat: Option to use accurate dotprod for VMMUL.
Eliminates Tekken 6 leg shaking.
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2019-08-05 11:44:52 -07:00 |
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Henrik Rydgård
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f49999efca
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Revert "ARM64 vmmul experiment: Disable if S and T matrices overlap."
This reverts commit c4d26dcb10.
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2019-06-06 09:34:23 +02:00 |
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Henrik Rydgård
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649b7a5671
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ARM64 vmmov experiment: Reduce precision by using FMUL+FADD instead of FMADD. May help #12082 and thus also #11179 and #9843.
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2019-06-05 00:02:32 +02:00 |
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Henrik Rydgård
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c4d26dcb10
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ARM64 vmmul experiment: Disable if S and T matrices overlap.
If this fixes anything in #12082, we have a regalloc bug I guess...
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2019-06-04 22:24:19 +02:00 |
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Henrik Rydgård
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7853c90abb
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JIT: Split VFPU_MTX disable options. To help with #9843
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2019-06-03 23:28:15 +02:00 |
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Unknown W. Brackets
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c773359095
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arm64jit: Tweak matrix vfpu overlap detect, etc.
Tried making changes to them to guess at issues for #9843, but didn't find
any. Still, I think these changes are worthwhile, if small.
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2019-06-02 22:10:20 -07:00 |
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Unknown W. Brackets
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1358a80aa6
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arm64jit: Fix avoidLoad handling for fpu regs.
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2019-06-02 22:03:06 -07:00 |
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Henrik Rydgård
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55b4b4b9e3
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Style fix
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2019-06-02 16:22:19 +02:00 |
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Henrik Rydgård
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6fd40332fd
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JitDisable: Add option to disable regalloc across instructions (flush after every instruction)
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2019-06-02 16:06:10 +02:00 |
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M4xw
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b9352354c9
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Masked PSP Memory support for the AArch64 Dynarec
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2019-04-15 12:07:57 +02:00 |
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Unknown W. Brackets
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a5214d0b1a
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Jit: Ignore high bit in vmfvc/vmtvc.
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2019-03-31 17:09:55 -07:00 |
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Unknown W. Brackets
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5749ae09d0
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interp: Correct vmfvc register behavior.
The target and source registers were completely wrong.
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2019-03-31 13:41:48 -07:00 |
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Unknown W. Brackets
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d5273f589a
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interp: Mask value in vpfxd.
The actual register ends up with only the lower 12 bits, which makes sense
since those are the only ones that do anything.
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2019-03-31 08:23:36 -07:00 |
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Unknown W. Brackets
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6178a1fb33
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Jit: Correct vocp prefix handling.
See #5549. Matches tests for various prefix settings.
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2019-02-23 09:15:26 -08:00 |
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Henrik Rydgård
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c80dd44da8
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ARM/ARM64: Ignore invalid immediate addresses in delay slots, which may be conditional.
Should do something in x86's safe mem too, but leaving for later.
Replaces #11824
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2019-02-23 10:15:09 +01:00 |
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Unknown W. Brackets
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d7f40afd9d
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interp: Correct vocp prefix handling.
Also, guess that vsocp also applies prefixes. See #5549.
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2019-02-21 19:02:16 -08:00 |
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