Unknown W. Brackets
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b6612edf67
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arm64: Use a cached rounding func for cvt.w.s.
This is much faster for this particular instruction, although not all
games even use it.
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2015-06-28 12:40:29 -07:00 |
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Unknown W. Brackets
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1c163e4817
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arm64: Avoid an ORR for c.ueq.
This is about 15% faster for this single, uncommon instruction on A57.
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2015-06-28 10:52:17 -07:00 |
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Unknown W. Brackets
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febe435946
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arm64: Use FP load/stores for non-reg pointers.
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2015-06-28 10:45:44 -07:00 |
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Unknown W. Brackets
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213ad4bcc9
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arm64: Cleanup branch code a tiny bit.
Want to make it clear that we can't kill W0 at this point (delay slots.)
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2015-06-28 09:28:54 -07:00 |
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Unknown W. Brackets
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0978aa4d5e
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arm64: Use msub for div/divu remainder.
Not really much faster, but less instructions at least.
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2015-06-28 09:05:39 -07:00 |
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Unknown W. Brackets
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0a5b1c030b
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arm64: Implement ext and ins.
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2015-06-28 08:45:17 -07:00 |
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Unknown W. Brackets
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daddb73f22
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arm64: Implement nor.
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2015-06-28 00:41:04 -07:00 |
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Unknown W. Brackets
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11a851a139
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arm64: Enable movz/movn.
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2015-06-28 00:41:04 -07:00 |
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Unknown W. Brackets
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223e55a453
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arm64: Undisable clz/clo, they work.
Also, avoid a temp in clo. It's the tiniest bit faster on A57, though
we'll see how it works out elsewhere. A bit clearer without the temp
imho.
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2015-06-28 00:41:03 -07:00 |
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Unknown W. Brackets
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81bc8107cf
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arm64: Use UBFX, not LSR, for slti sign check.
This is about 22% faster on the A57 (for just this one instruction, so not
a huge impact overall.) Makes sense that it would be since not arith.
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2015-06-28 00:41:03 -07:00 |
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Unknown W. Brackets
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fedbe645e0
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arm64: Use all immediate compares in safemem.
Ah, this is better.
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2015-06-27 00:22:09 -07:00 |
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Unknown W. Brackets
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3c29ec2051
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arm64: Optimize codesize in safemem path a bit.
Will only be used for scratchpad, I think.
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2015-06-27 00:22:04 -07:00 |
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Unknown W. Brackets
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fbd4db0fc4
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arm64: Add a safemem path.
This is probably not optimal but at least it works.
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2015-06-27 00:22:04 -07:00 |
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Unknown W. Brackets
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b3aa6d89e9
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Fix UBFX encoding (thanks SonicAdvance1.)
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2015-06-26 21:27:03 -07:00 |
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Henrik Rydgard
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e848247f88
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ARM64: Also save FP registers around the JIT dispatcher loop
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2015-06-14 13:03:46 +02:00 |
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Henrik Rydgard
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2c05334d47
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ARM64: Fix bug where we didn't save the FP registers correctly in the vertex decoder.
Also port a few ops from dolphin's ARM64 emitter.
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2015-06-14 12:56:44 +02:00 |
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Henrik Rydgård
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70fa830ba5
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Split out the ReplaceJalTo test logic.
This makes it so the IR, in the future, can work correctly for
replacements.
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2015-04-12 13:35:10 -07:00 |
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Henrik Rydgård
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d014d420db
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Unify JitOptions across the backends.
This is required to make ExtractIR not a member of the various backends.
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2015-04-12 11:41:26 -07:00 |
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Henrik Rydgård
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81dec36da8
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Use an accessor to read the compilerPC.
In the IR it will be read from the block.
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2015-04-11 01:14:37 -07:00 |
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Henrik Rydgård
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a897723e6a
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Separate out jit reading nearby instructions.
This makes it easier to use an IR for these things, or remove them.
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2015-04-11 00:53:24 -07:00 |
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Unknown W. Brackets
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b0d291032d
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armjit Avoid cfc1/mfc1 to $0.
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2015-04-07 18:30:36 -07:00 |
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Unknown W. Brackets
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788b9d78f8
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jit: Avoid a super unlikely write to zero.
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2015-04-07 18:20:37 -07:00 |
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Henrik Rydgård
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a8c2d0945a
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ARM64: lwl: Pass INVALID_REG to be sure SCRATCH1 doesn't get overwritten...
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2015-04-06 18:13:41 +02:00 |
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Henrik Rydgård
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13c9390c53
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ARM64: Emitter fix, disable swl/swr/lwl/lwr again fully
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2015-04-06 18:13:38 +02:00 |
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Henrik Rydgård
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fbaffdceab
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Remove some outdated comments, minor stuff
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2015-04-06 18:13:36 +02:00 |
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