Unknown W. Brackets
fc476020ba
riscv: Improve immediate generation.
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Use compressed instructions more, better jumps when outside PC 32-bit
range.
2023-08-12 09:37:02 -07:00
Unknown W. Brackets
4b9011e475
riscv: Reduce call bloat using temps.
2023-08-08 23:17:32 -07:00
Unknown W. Brackets
26a527bdf8
riscv: Implement float/int conversion.
2023-07-30 00:45:51 -07:00
Unknown W. Brackets
76e3246065
riscv: Reduce jit codesize a bit.
2023-07-23 18:01:00 -07:00
Unknown W. Brackets
47b81985bd
riscv: Initial untested dispatcher.
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The minimum to actually, probably, running code. Pretty slow.
2023-07-23 18:01:00 -07:00
Unknown W. Brackets
030a27f15d
riscv: Stop considering bitmanip "B".
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Apparently it's not being called B anymore and B is still reserved.
2023-07-23 14:41:08 -07:00
Unknown W. Brackets
e0eace505b
riscv: Fix cases of SetRegToImmediate().
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Was using the wrong value for AUIPC, causing assertion failures and wrong
values. Also needed to handle sign-extend more carefully.
2023-07-23 14:41:08 -07:00
Unknown W. Brackets
27e60a9f2e
riscv: Sum weighted matrices in vertexjit.
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Not yet doing pos/norm, so not used yet.
2023-02-16 18:32:58 -08:00
Unknown W. Brackets
04ce3a0572
riscv: Allow subset of B extension to be used.
2023-02-16 16:09:22 -08:00
Unknown W. Brackets
684aa75388
riscv: Include morph in vertexjit.
2023-02-14 20:20:55 -08:00
Unknown W. Brackets
1ec33ddc04
riscv: Use __riscv_flush_icache() on Linux.
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This seems to perhaps clear icache on all harts. Otherwise crashing is
seen. Not sure what to do on other platforms.
2023-02-14 19:59:42 -08:00
Unknown W. Brackets
0b05d20c0a
riscv: Fix poison with compressed instructions.
2023-02-12 13:02:55 -08:00
Unknown W. Brackets
89c18d8077
riscv: Cleanup missing Poison, Crash.
2023-02-12 12:10:29 -08:00
Unknown W. Brackets
a0ef9ce103
riscv: Add half-float encodings.
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These are simple.
2023-01-29 16:31:01 -08:00
Unknown W. Brackets
dcd83c1e47
riscv: Detect Zicsr with cpu_features.
2023-01-29 15:24:41 -08:00
Unknown W. Brackets
3bc2450b5e
riscv: Add bitmanip instructions to emitter ( #16832 )
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* riscv: Cleanup emitter, add bitmanip detect.
Better to encode using Funct7::ZERO, and obviously for SRA.
* riscv: Add bitmanip instructions to emitter.
2023-01-22 21:37:47 +01:00
Unknown W. Brackets
2aeee83971
riscv: Add vector transfer instructions.
2023-01-22 00:17:40 -08:00
Unknown W. Brackets
c99eb18f33
riscv: Add vector mask instructions.
2023-01-21 23:43:28 -08:00
Unknown W. Brackets
88de043329
riscv: Add vector reduce instructions.
2023-01-21 22:35:38 -08:00
Unknown W. Brackets
2a7bdbf802
riscv: Add vector float move/compare/unary.
2023-01-21 22:05:13 -08:00
Unknown W. Brackets
f0796676fd
riscv: Add vector float arith/mul funcs.
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Including all the fused multiplies.
2023-01-21 20:48:49 -08:00
Unknown W. Brackets
a1ca291362
riscv: Add vector fixed-point arith instructions.
2023-01-21 20:23:10 -08:00
Unknown W. Brackets
a313e440b4
riscv: Add vector integer move/broadcast.
2023-01-21 19:46:50 -08:00
Unknown W. Brackets
6f78f2a2d2
riscv: Add vector integer muliplies.
2023-01-21 19:46:34 -08:00
Unknown W. Brackets
b3be901557
riscv: Add vector bitwise/compare funcs.
2023-01-21 19:36:22 -08:00
