izzy/ppsspp
0
0
Fork 0
mirror of https://github.com/izzy2lost/ppsspp.git synced 2026-03-10 12:43:04 -07:00
Code Issues Packages Projects Releases Wiki Activity

x86jit: Cache fpcond in a register.

Browse Source 
Mostly to match armjit.
This commit is contained in:
Unknown W. Brackets
2014-06-27 22:03:00 -07:00
parent d2f43889a0
commit acad2e1763
5 changed files with 103 additions and 21 deletions
Download Patch File Download Diff File Expand all files Collapse all files
Core/MIPS/ARM/ArmCompFPU.cpp
+31 -12
View File
@@ -341,15 +341,25 @@ void Jit::Comp_mxc1(MIPSOpcode op)
case 2: //cfc1
if (fs == 31) {
gpr.MapDirtyIn(rt, MIPS_REG_FPCOND);
LDR(gpr.R(rt), CTXREG, offsetof(MIPSState, fcr31));
if (gpr.IsImm(MIPS_REG_FPCOND)) {
gpr.MapReg(rt, MAP_DIRTY | MAP_NOINIT);
LDR(gpr.R(rt), CTXREG, offsetof(MIPSState, fcr31));
if (gpr.GetImm(MIPS_REG_FPCOND) & 1) {
ORI2R(gpr.R(rt), gpr.R(rt), 0x1 << 23, SCRATCHREG2);
} else {
ANDI2R(gpr.R(rt), gpr.R(rt), ~(0x1 << 23), SCRATCHREG2);
}
} else {
gpr.MapDirtyIn(rt, MIPS_REG_FPCOND);
LDR(gpr.R(rt), CTXREG, offsetof(MIPSState, fcr31));
#ifdef HAVE_ARMV7
BFI(gpr.R(rt), gpr.R(MIPS_REG_FPCOND), 23, 1);
BFI(gpr.R(rt), gpr.R(MIPS_REG_FPCOND), 23, 1);
#else
AND(SCRATCHREG1, gpr.R(MIPS_REG_FPCOND), Operand2(1)); // Just in case
ANDI2R(gpr.R(rt), gpr.R(rt), ~(0x1 << 23), SCRATCHREG2); // SCRATCHREG2 won't be used, this turns into a simple BIC.
ORR(gpr.R(rt), gpr.R(rt), Operand2(SCRATCHREG1, ST_LSL, 23));
AND(SCRATCHREG1, gpr.R(MIPS_REG_FPCOND), Operand2(1)); // Just in case
ANDI2R(gpr.R(rt), gpr.R(rt), ~(0x1 << 23), SCRATCHREG2); // SCRATCHREG2 won't be used, this turns into a simple BIC.
ORR(gpr.R(rt), gpr.R(rt), Operand2(SCRATCHREG1, ST_LSL, 23));
#endif
}
} else if (fs == 0) {
gpr.SetImm(rt, MIPSState::FCR0_VALUE);
} else {
@@ -365,9 +375,14 @@ void Jit::Comp_mxc1(MIPSOpcode op)
return;
case 6: //ctc1
if (fs == 31)
{
gpr.MapDirtyIn(MIPS_REG_FPCOND, rt);
if (fs == 31) {
bool wasImm = gpr.IsImm(rt);
if (wasImm) {
gpr.SetImm(MIPS_REG_FPCOND, (gpr.GetImm(rt) >> 23) & 1);
gpr.MapReg(rt);
} else {
gpr.MapDirtyIn(MIPS_REG_FPCOND, rt);
}
// Hardware rounding method.
// Left here in case it is faster than conditional method.
/*
@@ -388,12 +403,16 @@ void Jit::Comp_mxc1(MIPSOpcode op)
// Update MIPS state
// TODO: Technically, should mask by 0x0181FFFF. Maybe just put all of FCR31 in the reg?
STR(gpr.R(rt), CTXREG, offsetof(MIPSState, fcr31));
if (!wasImm) {
#ifdef HAVE_ARMV7
UBFX(gpr.R(MIPS_REG_FPCOND), gpr.R(rt), 23, 1);
UBFX(gpr.R(MIPS_REG_FPCOND), gpr.R(rt), 23, 1);
#else
MOV(SCRATCHREG1, Operand2(gpr.R(rt), ST_LSR, 23));
AND(gpr.R(MIPS_REG_FPCOND), SCRATCHREG1, Operand2(1));
MOV(SCRATCHREG1, Operand2(gpr.R(rt), ST_LSR, 23));
AND(gpr.R(MIPS_REG_FPCOND), SCRATCHREG1, Operand2(1));
#endif
}
} else {
Comp_Generic(op);
}
return;
}