diff --git a/Core/Config.cpp b/Core/Config.cpp
index 863184e3df..5f6d8c1f61 100644
--- a/Core/Config.cpp
+++ b/Core/Config.cpp
@@ -90,7 +90,7 @@ void Config::Load(const char *iniFileName)
 	cpu->Get("Jit", &bJit, true);
 #endif
 	cpu->Get("SeparateCPUThread", &bSeparateCPUThread, false);
-	cpu->Get("SeparateIOThread", &bSeparateIOThread, true);
+	cpu->Get("SeparateIOThread", &bSeparateIOThread, false);
 	cpu->Get("FastMemory", &bFastMemory, false);
 	cpu->Get("CPUSpeed", &iLockedCPUSpeed, false);
 
diff --git a/Core/CoreTiming.cpp b/Core/CoreTiming.cpp
index a080adb17e..1879a4869f 100644
--- a/Core/CoreTiming.cpp
+++ b/Core/CoreTiming.cpp
@@ -74,7 +74,7 @@ volatile u32 hasTsEvents = false;
 // as we can already reach that structure through a register.
 int slicelength;
 
-s64 globalTimer;
+MEMORY_ALIGNED16(s64) globalTimer;
 s64 idledCycles;
 
 static std::recursive_mutex externalEventSection;
diff --git a/Core/MIPS/MIPSAnalyst.cpp b/Core/MIPS/MIPSAnalyst.cpp
index 5f16b37c37..1f0cf6ff57 100644
--- a/Core/MIPS/MIPSAnalyst.cpp
+++ b/Core/MIPS/MIPSAnalyst.cpp
@@ -141,7 +141,7 @@ namespace MIPSAnalyst
 				int rd = MIPS_GET_RD(op);
 
 				if (
-					((info & IN_RS) && !(info & IN_RS_ADDR) && (rs == reg)) ||
+					((info & IN_RS) && (info & IN_RS_ADDR) == IN_RS && (rs == reg)) ||
 					((info & IN_RT) && (rt == reg)))
 				{
 					if (regAnal[reg].firstRead == -1)
diff --git a/Core/MIPS/MIPSCodeUtils.cpp b/Core/MIPS/MIPSCodeUtils.cpp
index 91a344e8e6..fad4dddb63 100644
--- a/Core/MIPS/MIPSCodeUtils.cpp
+++ b/Core/MIPS/MIPSCodeUtils.cpp
@@ -114,6 +114,9 @@ namespace MIPSCodeUtils
 					sure = _RS == 0;
 					takeBranch = false;
 					break;
+
+				default:
+					sure = false;
 				}
 
 				if (sure && takeBranch)
diff --git a/GPU/GPUCommon.cpp b/GPU/GPUCommon.cpp
index b4001a338f..d013a08256 100644
--- a/GPU/GPUCommon.cpp
+++ b/GPU/GPUCommon.cpp
@@ -558,7 +558,7 @@ void GPUCommon::ProcessEvent(GPUEvent ev) {
 		break;
 
 	default:
-		ERROR_LOG(G3D, "Unexpected GPU event type: %d", ev);
+		ERROR_LOG(G3D, "Unexpected GPU event type: %d", (int)ev);
 	}
 }
 
diff --git a/GPU/GPUCommon.h b/GPU/GPUCommon.h
index 86f3a0b2bd..43ae9a5530 100644
--- a/GPU/GPUCommon.h
+++ b/GPU/GPUCommon.h
@@ -1,8 +1,16 @@
 #pragma once
 
+#include "Common/Common.h"
 #include "Core/ThreadEventQueue.h"
 #include "GPU/GPUInterface.h"
 
+#if defined(ANDROID)
+#include <atomic>
+#elif defined(_M_SSE)
+#include <xmmintrin.h>
+#pragma warning(disable:4799)
+#endif
+
 typedef ThreadEventQueue<GPUInterface, GPUEvent, GPUEventType, GPU_EVENT_INVALID, GPU_EVENT_SYNC_THREAD, GPU_EVENT_FINISH_EVENT_LOOP> GPUThreadEventQueue;
 
 class GPUCommon : public GPUThreadEventQueue
@@ -37,10 +45,15 @@ public:
 	virtual void ReapplyGfxState();
 
 	virtual u64 GetTickEstimate() {
-#ifndef _M_X64
-		lock_guard guard(curTickEstLock_);
-#endif
+#if defined(_M_X64) || defined(ANDROID)
 		return curTickEst_;
+#elif defined(_M_SSE)
+		__m64 result = *(__m64 *)&curTickEst_;
+		return *(u64 *)&result;
+#else
+		lock_guard guard(curTickEstLock_);
+		return curTickEst_;
+#endif
 	}
 
 protected:
@@ -94,14 +107,23 @@ protected:
 	bool interruptsEnabled_;
 
 	// For CPU/GPU sync.
-	volatile u64 curTickEst_;
+#ifdef ANDROID
+	std::atomic<u64> curTickEst_;
+#else
+	volatile MEMORY_ALIGNED16(u64) curTickEst_;
 	recursive_mutex curTickEstLock_;
+#endif
 
 	virtual void UpdateTickEstimate(u64 value) {
-#ifndef _M_X64
-		lock_guard guard(curTickEstLock_);
-#endif
+#if defined(_M_X64) || defined(ANDROID)
 		curTickEst_ = value;
+#elif defined(_M_SSE)
+		__m64 result = *(__m64 *)&value;
+		*(__m64 *)&curTickEst_ = result;
+#else
+		lock_guard guard(curTickEstLock_);
+		curTickEst_ = value;
+#endif
 	}
 
 public:
diff --git a/ext/disarm.cpp b/ext/disarm.cpp
index cada7c3ef0..4c0f192272 100644
--- a/ext/disarm.cpp
+++ b/ext/disarm.cpp
@@ -142,7 +142,7 @@ bool DisasmVFP(uint32_t op, char *text) {
 				if ((op & 0xFFF) != 0xA10)
 					break;
 				if (op == 0xEEF1FA10) {
-					sprintf(text, "VMRS APSR", cond);
+					sprintf(text, "VMRS%s APSR", cond);
 				} else {
 					sprintf(text, "VMRS%s r%i", cond, (op >> 12) & 0xF);
 				}