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150 Commits
Author SHA1 Message Date
Vincent Pelletier 099e6c9ab6 docs/DSP: Trivial adjustment to BLOOP{,I} sub-operation order 
Noticed while tracing in a BLOOP using DSPSpy with $st{0..3} unmasked.
BLOOPI assumed to follow the pattern.
 2022-09-30 11:07:41 +00:00
Pokechu22 f47dfc3dba docs/DSP: Update version and history 
The GFDL requires the history section to be updated.
 2022-06-01 22:26:59 -07:00
Pokechu22 24a339f437 docs/DSP: Explain 16-bit and 40-bit modes 2022-06-01 22:25:59 -07:00
Pokechu22 d297ab18e6 docs/DSP: Add notes highlighting the difference between 'LS and 'SL 2022-06-01 22:25:59 -07:00
Pokechu22 0dd181f461 docs/DSP: Add missing dollar signs in shift instruction operation sections 2022-05-31 16:26:55 -07:00
Pokechu22 7c63bd1893 docs/DSP: Fix inconsistency with ADDI and CMPI 
We don't have anything called $amD, though we do have $acsD.  However, these instructions affect flags based on the whole accumulator, so it's better to just use $acD.
 2022-05-29 15:00:09 -07:00
Pokechu22 4dc7208195 docs/DSP: Fix typo with arithmetic instructions that take a 16-bit immediate 
These instructions used an 'r' in their bit list, but a 'd' in the operands.
 2022-05-29 15:00:09 -07:00
Pokechu22 b349254ff4 docs/DSP: Document the behavior when main and extended opcodes both write to the same register (the write backlog) 
For more information, ApplyWriteBackLog, WriteToBackLog, and ZeroWriteBackLog were added in b787f5f8f7 and the explanatory comment was added in fd40513fed, although it did not mention the specific instructions that could trigger this edge case. The statements about which registers can be written by main opcodes and extension opcodes are based on my own checking of all instructions in the manual.
 2022-05-29 15:00:09 -07:00
Pokechu22 bb01ba60d6 docs/DSP: Fix typo in 'NOP comment 2022-05-29 15:00:09 -07:00
Pokechu22 83aabbbece docs/DSP: Clarify LRS note 
$acS.h was a typo, which has been replaced with $acD.h.
 2022-05-29 15:00:09 -07:00
Pokechu22 ce4aba7d5e docs/DSP: Rename CMPAR to CMPAXH 2022-05-27 18:22:38 -07:00
Pokechu22 0531e51e39 docs/DSP: Fix "ILLR" typo in Instruction Memory section 2022-05-21 22:59:04 -07:00
xperia64 534d92d2c5 Add tested bootloading transfer size 2022-05-14 23:12:53 -04:00
Pokechu22 44129dda4c dsp_rom: Add version numbers and hashes to VerifyRoms and readme 2021-08-22 10:49:46 -07:00
Pokechu22 a5e2a0d973 dsp_rom: Remove illegal use of AX with SRS 2021-08-22 10:49:46 -07:00
Tillmann KarrasandPokechu22 c881f4db22 dsp_rom: add pseudo code and fix small accuracy issues 
Doesn't fix anything, hence not upstreaming this.
 2021-08-22 10:49:46 -07:00
Pokechu22 d0b40528e5 dsp_rom: Fix readme eols and trailing whitespace 2021-08-22 10:49:46 -07:00
Pokechu22 4fa9517ba3 docs/DSP: Update version and history 
The GFDL requires the history section to be updated.
 2021-08-21 17:07:14 -07:00
Pokechu22 9ef388f1c3 docs/DSP: NEG can set overflow and carry 2021-08-21 17:07:14 -07:00
Pokechu22 602163b623 docs/DSP: Fix typo with MULCMVZ and MULCMV 2021-08-21 17:07:14 -07:00
Pokechu22 c51c339424 docs/DSP: Document initialization process 2021-08-21 17:07:14 -07:00
Pokechu22 5bf59f3ce4 docs/DSP: A failed RETcc only inceases PC by 1, not 2 
This is because RETcc is a single-word instruction.
 2021-08-21 17:07:14 -07:00
Pokechu22 1b84721b7f docs/DSP: Add RTIcc 2021-08-21 17:07:14 -07:00
Pokechu22 5611bd8f23 docs/DSP: Change conditional names to match Dolphin 2021-08-21 17:07:14 -07:00
Pokechu22 af10eab938 docs/DSP: Split SRSH from SRS 2021-08-21 17:07:14 -07:00