Commit Graph

73 Commits

Author SHA1 Message Date
Ben Ingram
e6c2c85df5 Fixes for UDIM VTs in texture editor
UDIMs use transformed UVs, account for these when computing visible regions
#rb none
#jira none

[CL 15926164 by Ben Ingram in ue5-main branch]
2021-04-05 21:56:26 -04:00
Jeremy Moore
81a5b31997 Fix auto merge error
#jira none
#rb trivial

[CL 15922889 by Jeremy Moore in ue5-main branch]
2021-04-05 16:35:53 -04:00
jeremy moore
e164217933 #jira UE-112852
Integrate virutal texture allocator improvements from main.
[FYI] ben.ingram
#lockdown kevin.ortegren

#ROBOMERGE-SOURCE: CL 15922154 in //UE5/Release-5.0-EarlyAccess/...
#ROBOMERGE-BOT: STARSHIP (Release-5.0-EarlyAccess -> Main) (v786-15839533)

[CL 15922638 by jeremy moore in ue5-main branch]
2021-04-05 16:16:29 -04:00
Ben Ingram
ee8539464d Fixes for VT texture viewer
- Account for VT requests now encoding vLevel+1
- Fix sampling in shader when explicit mip level is not given
#rb none
#jira none

[CL 15905062 by Ben Ingram in ue5-main branch]
2021-04-02 15:46:47 -04:00
Ben Ingram
72b67d6af6 Update logic for dealing with VT wrap
- Now try to map both wrapped/unwrapped address when processing a wrapped address
- Previously there was nothing to map tiles to the original vAddress
#rb none
#jira FROST-1581

[CL 15857083 by Ben Ingram in ue5-main branch]
2021-03-29 20:23:32 -04:00
Ben Ingram
60478d3652 VT allocator improvements
- Check partially allocated block for fit, don't need to start with a completely free block for allocations
- Try to use the lowest possible vAddress for new allocations, this reduces the texture area covered by allocations
- Page table is no longer required to be square power-2 texture, instead allow it to grow organically as allocated area increases
- Allocator starts with maximum-sized block and tracks allocated area, no longer needs special logic to 'grow'
- Rectangular allocated VTs now mip based on min-size rather than max-size, relaxes alignment requirements and allows better packing
#rb jeremy.moore
#jira none

[CL 15825578 by Ben Ingram in ue5-main branch]
2021-03-25 12:40:35 -04:00
danny couture
9ac59bee66 Add meaningful Insights trace affecting either map loading or PIE
#rb Francis.Hurteau

[CL 15777110 by danny couture in ue5-main branch]
2021-03-23 10:58:12 -04:00
Yuriy ODonnell
da38c78f19 Added TRACE_CPUPROFILER_EVENT_SCOPE-s in various parts of rendering code that can take non-trivial time.
#preflight 60578088c118270001c6367f

[CL 15756286 by Yuriy ODonnell in ue5-main branch]
2021-03-21 13:53:35 -04:00
Ben Ingram
e1a07fc4a8 r.VT.ListPhysicalPools also reports total memory usage
#rb none
#jira none

[CL 15741593 by Ben Ingram in ue5-main branch]
2021-03-18 16:57:33 -04:00
Ben Ingram
d4bba48214 Add name of material to AllocateVT as debug aid
- Rework hashing of FAllocatedVTDescription to be more explicit about hashing each individual member, don't hash the debug name
#rb none
#jira none

[CL 15732300 by Ben Ingram in ue5-main branch]
2021-03-17 19:47:18 -04:00
Jeremy Moore
a03368976e #jira FROST-1315
Ensure that we mask off unwanted bits in the UDIM wrapped address.
Fixes bugs in VT mapping.
#rb ben.ingram

[CL 15728315 by Jeremy Moore in ue5-main branch]
2021-03-17 14:59:07 -04:00
Jeremy Moore
f8c7aa88b0 Fix VT page table memory stat not being updated after first alloc for each space.
Added AVT indirection texture into page table memory stat.
#fyi ben.ingram
#rb none

[CL 15701048 by Jeremy Moore in ue5-main branch]
2021-03-15 18:01:26 -04:00
Marc Audy
bc88b73a29 Merge Release-Engine-Staging to Main @ CL# 15151250
Represents UE4/Main @ 15133763

[CL 15158774 by Marc Audy in ue5-main branch]
2021-01-21 16:22:06 -04:00
Jeremy Moore
0a40a793e9 Reduce log spam for VT. Only report dropping requests in verbose mode since it is expected behavior.
#rb none
#fyi Ben.Ingram

[CL 15091162 by Jeremy Moore in ue5-main branch]
2021-01-14 15:20:21 -04:00
Ben Ingram
c3579c58d2 Add FTaskTagScopes to VT tasks
#rb none
#jira none

[CL 14811680 by Ben Ingram in ue5-main branch]
2020-11-24 21:47:55 -04:00
Marc Audy
a7f9391231 Merge UE5/Release-Engine-Staging @ 14811410 to UE5/Main
This represents UE4/Main @ 14768117

For ReleaseObjectVersion.h
#lockdown Marcus.Wassmer

[CL 14811440 by Marc Audy in ue5-main branch]
2020-11-24 18:42:39 -04:00
Jeremy Moore
8fe393561d Ensure that locked pages are still flushed after a virtual texture flush command.
Previously for streaming pages, the request would return pending, but because the page is mapped, no subsequent request would occur.
#rb none

[CL 14738087 by Jeremy Moore in ue5-main branch]
2020-11-12 16:08:00 -04:00
Jeremy Moore
8464dd49fb #jira UESP-4125
Always test if page is mapped instead of assuming it isn't in one case.
This is a placeholder solution for a VT mapping crash while I investigate how the logic is failing here.
#rb none

[CL 14700400 by Jeremy Moore in ue5-main branch]
2020-11-10 12:09:59 -04:00
Ben Ingram
f2d617e356 Compute VT page wrapping relative to the highest resolution mip, rather than the current mip...this allows us to preserve the correct wrapped vAddress, which also needs to be relative to the top mip
#rb none
#jira none

[CL 14659977 by Ben Ingram in ue5-main branch]
2020-11-04 21:14:19 -04:00
Ben Ingram
15608b983f Restore a VT check that was previously removed...check is actually valid, was removed due to other bugs
#rb none
#jira none

[CL 14617565 by Ben Ingram in ue5-main branch]
2020-10-29 19:43:10 -04:00
Ben Ingram
34ec7481a4 Fix wrapped VT address computation
#rb none
#jira none

[CL 14615016 by Ben Ingram in ue5-main branch]
2020-10-29 16:21:58 -04:00
Marc Audy
68150e0be7 Merge UE5/Release-Engine-Staging to UE5/Main @ 14611496
This represents UE4/Main @ 14594913

[CL 14612291 by Marc Audy in ue5-main branch]
2020-10-29 13:38:15 -04:00
Ben Ingram
cfe2e82b9b Fix bias handling for mapping resident pages of newly allocated VTs
#rb none
#jira UESP-4017

[CL 14582238 by Ben Ingram in ue5-main branch]
2020-10-26 17:58:40 -04:00
zach bethel
2bc88676d6 Converted virtual texture system and GPU lightmass to RDG.
#rb yujiang.wang, jeremy.moore
#jira none

[CL 14581416 by zach bethel in ue5-main branch]
2020-10-26 16:44:44 -04:00
Ben Ingram
de1bc01ce9 Fix logic used to wrap UDIM VT coordinates during CPU update
- Need to make sure wrapped vAddress is properly used in all cases, otherwise can end up with duplicate/inconsistent page mappings
#rb none
#jira UESP-4030, UESP-4017

[CL 14580045 by Ben Ingram in ue5-main branch]
2020-10-26 15:28:18 -04:00