- If we output < 4 instance we are writing to memory before the allocation
- Data buffers are allocated 16 byte aligned and each component is aligned to 16 bytes so we can therefore just loop until all components are written
#rb rob.krajcarski
[CL 29443739 by stu mckenna in ue5-main branch]
* TRACE_CPUPROFILER_EVENT_SCOPE(ScopeName) --> to be used with a plain text as scope name (not a string!). If the parameter is a string ("abc" or TEXT("abc")), the quotes (and the TEXT prefix) will be included in the actual timer name.
* TRACE_CPUPROFILER_EVENT_SCOPE_STR("scope name") --> to be used with a static string (const ANSICHAR* or const TCHAR*); ex: when the scope name needs to include a space char
* TRACE_CPUPROFILER_EVENT_SCOPE_TEXT(*MyScopeName) --> to be used with a dynamic string (const ANSICHAR* or const TCHAR*)
See also the comments for these macros in ProfilingDebugging\CpuProfilerTrace.h.
#rb Catalin.Dragoiu
[CL 28337510 by ionut matasaru in ue5-main branch]
-Cleans up the checks of the constant buffers at runtime
-Removes the search for conflicts that was exclusive to exec_index & i2f and makes sure merging exec_index only considers temp registers
-Adds an EVVM assembly string representation in the Generated Code view
-fixes random_addi implementation that was sharing the buffer increment value between the random seed and the addition operand
-fixes a OOB access/stomp when dealing with newly identified unused ext function output operands
#jira UE-193006, UE-193112
#rb stu.mckenna
[CL 27182518 by rob krajcarski in ue5-main branch]
Fixing Same Frame Reads. We currently write to local data and then publish in post simulate, however post simulate tick can be moved to the end to the frame which means it's impossible to get same frame reads in the subsequent tick phases.
- Moved Begin/End simulate of write DI dataset to new Pre/Post stage tick path.
- Write DI now publishes from post stage so made publishing to data channel data threadsafe.
- Write DI now grabs it's data channel data once in presimulate rather than in post simulate.
- Fixed issue preventing proper init of Pre/Post simulate tick lists.
Write and Append now updating NumInstances via atomic in post stage to fix threadsafety with parallem VM exec.
Added optimized path through Append() in cases where we're emitting every particle.
This required a slight tweak to the DI handlers.
#rb Stu.Mckenna,Rob.Krajcarski
#preflight 646620cb063e77985c3efc3f
[CL 25525227 by simon tovey in ue5-main branch]
