From e3b71c4611f35d7f4f14f5703debc4a81c70303d Mon Sep 17 00:00:00 2001 From: k2154 Date: Wed, 20 Aug 2025 22:37:00 +0900 Subject: [PATCH] Android project - Added ShuffleLanes.h used in VixlHelpers.cpp(armSHUFPS, armPSHUFD) --- app/src/main/cpp/common/CMakeLists.txt | 9 +- .../main/cpp/common/emitter/x86emitter.cpp | 1 + app/src/main/cpp/common/emitter/x86types.h | 5 +- app/src/main/cpp/pcsx2/CMakeLists.txt | 8 +- app/src/main/cpp/pcsx2/Common.h | 1 + app/src/main/cpp/pcsx2/Pcsx2Config.cpp | 2 + app/src/main/cpp/pcsx2/R3000A.h | 2 +- app/src/main/cpp/pcsx2/R5900.h | 2 +- app/src/main/cpp/pcsx2/VUDef.h | 2 + app/src/main/cpp/pcsx2/arm64/ShuffleLanes.h | 272 ++++++++++++++++++ app/src/main/cpp/pcsx2/arm64/Vif_UnpackNEON.h | 2 +- .../arm64/VixlHelpers.cpp} | 82 ++---- .../arm64/VixlHelpers.h} | 12 +- .../cpp/pcsx2/{ => arm64}/cpuRegistersPack.h | 4 + app/src/main/cpp/pcsx2/vtlbDef.h | 2 +- app/src/main/cpp/pcsx2/x86/BaseblockEx.h | 2 +- app/src/main/cpp/pcsx2/x86/iCOP0.cpp | 6 +- app/src/main/cpp/pcsx2/x86/iFPU.cpp | 14 +- app/src/main/cpp/pcsx2/x86/iFPUd.cpp | 18 +- app/src/main/cpp/pcsx2/x86/iR3000A.cpp | 10 +- app/src/main/cpp/pcsx2/x86/iR3000A.h | 2 +- app/src/main/cpp/pcsx2/x86/iR3000Atables.cpp | 2 +- app/src/main/cpp/pcsx2/x86/ix86-32/iR5900.cpp | 7 +- .../cpp/pcsx2/x86/ix86-32/iR5900MultDiv.cpp | 2 +- .../main/cpp/pcsx2/x86/ix86-32/recVTLB.cpp | 25 +- .../main/cpp/pcsx2/x86/microVU_Execute.inl | 16 +- 26 files changed, 380 insertions(+), 130 deletions(-) create mode 100644 app/src/main/cpp/pcsx2/arm64/ShuffleLanes.h rename app/src/main/cpp/{common/arm64/AsmHelpers.cpp => pcsx2/arm64/VixlHelpers.cpp} (94%) rename app/src/main/cpp/{common/arm64/AsmHelpers.h => pcsx2/arm64/VixlHelpers.h} (97%) rename app/src/main/cpp/pcsx2/{ => arm64}/cpuRegistersPack.h (87%) diff --git a/app/src/main/cpp/common/CMakeLists.txt b/app/src/main/cpp/common/CMakeLists.txt index ae2b605..1d9c463 100644 --- a/app/src/main/cpp/common/CMakeLists.txt +++ b/app/src/main/cpp/common/CMakeLists.txt @@ -124,8 +124,6 @@ if(_M_X86) ) else() target_sources(common PRIVATE - arm64/AsmHelpers.cpp - arm64/AsmHelpers.h emitter/x86emitter.cpp emitter/x86emitter.h emitter/x86types.h @@ -216,7 +214,6 @@ if(NOT WIN32) endif() if(ANDROID) - target_link_libraries(common INTERFACE vixl) target_link_libraries(common PRIVATE ${LIBC_LIBRARIES} jpeg @@ -248,11 +245,7 @@ endif() fixup_file_properties(common) target_compile_features(common PUBLIC cxx_std_20) -if(ANDROID) - target_include_directories(common PUBLIC ../3rdparty/include ../3rdparty/vixl/include ../) -else() - target_include_directories(common PUBLIC ../3rdparty/include ../) -endif() +target_include_directories(common PUBLIC ../3rdparty/include ../3rdparty/vixl/include ../) target_compile_definitions(common PUBLIC "${PCSX2_DEFS}") target_compile_options(common PRIVATE "${PCSX2_WARNINGS}") diff --git a/app/src/main/cpp/common/emitter/x86emitter.cpp b/app/src/main/cpp/common/emitter/x86emitter.cpp index dd613ad..6c0084d 100644 --- a/app/src/main/cpp/common/emitter/x86emitter.cpp +++ b/app/src/main/cpp/common/emitter/x86emitter.cpp @@ -18,6 +18,7 @@ #if defined(__ANDROID__) #include "common/emitter/x86types.h" + #else #include "common/emitter/internal.h" #endif diff --git a/app/src/main/cpp/common/emitter/x86types.h b/app/src/main/cpp/common/emitter/x86types.h index cf8d0fe..310f56b 100644 --- a/app/src/main/cpp/common/emitter/x86types.h +++ b/app/src/main/cpp/common/emitter/x86types.h @@ -6,7 +6,10 @@ #include "common/Threading.h" #include "common/Assertions.h" #include "common/Pcsx2Defs.h" -#include "common/arm64/AsmHelpers.h" + +#include "vixl/aarch64/constants-aarch64.h" +#include "vixl/aarch64/macro-assembler-aarch64.h" +namespace a64 = vixl::aarch64; static const uint iREGCNT_XMM = 16; #if defined(__ANDROID__) diff --git a/app/src/main/cpp/pcsx2/CMakeLists.txt b/app/src/main/cpp/pcsx2/CMakeLists.txt index 0561aed..a7d0226 100644 --- a/app/src/main/cpp/pcsx2/CMakeLists.txt +++ b/app/src/main/cpp/pcsx2/CMakeLists.txt @@ -1056,13 +1056,13 @@ set(pcsx2x86Headers set(pcsx2arm64Sources arm64/Vif_Dynarec.cpp arm64/Vif_UnpackNEON.cpp -# arm64/AsmHelpers.cpp + arm64/VixlHelpers.cpp # arm64/RecStubs.cpp ) -#set(pcsx2arm64Headers -# arm64/AsmHelpers.h -#) +set(pcsx2arm64Headers + arm64/VixlHelpers.h +) # These ones benefit a lot from LTO set(pcsx2LTOSources diff --git a/app/src/main/cpp/pcsx2/Common.h b/app/src/main/cpp/pcsx2/Common.h index 244b534..c8032d5 100644 --- a/app/src/main/cpp/pcsx2/Common.h +++ b/app/src/main/cpp/pcsx2/Common.h @@ -3,6 +3,7 @@ #pragma once +#include "arm64/VixlHelpers.h" #include "common/Pcsx2Defs.h" static const u32 BIAS = 2; // Bus is half of the actual ps2 speed diff --git a/app/src/main/cpp/pcsx2/Pcsx2Config.cpp b/app/src/main/cpp/pcsx2/Pcsx2Config.cpp index 15d07e7..6a0a000 100644 --- a/app/src/main/cpp/pcsx2/Pcsx2Config.cpp +++ b/app/src/main/cpp/pcsx2/Pcsx2Config.cpp @@ -603,6 +603,8 @@ Pcsx2Config::CpuOptions::CpuOptions() VU0FPCR = DEFAULT_VU_FP_CONTROL_REGISTER; VU1FPCR = DEFAULT_VU_FP_CONTROL_REGISTER; ExtraMemory = false; + //// + g_cpuRegistersPack.Cpu = *this; } void Pcsx2Config::CpuOptions::ApplySanityCheck() diff --git a/app/src/main/cpp/pcsx2/R3000A.h b/app/src/main/cpp/pcsx2/R3000A.h index 85bd37d..a2783cc 100644 --- a/app/src/main/cpp/pcsx2/R3000A.h +++ b/app/src/main/cpp/pcsx2/R3000A.h @@ -3,7 +3,7 @@ #pragma once -#include "cpuRegistersPack.h" +#include "arm64/VixlHelpers.h" #ifndef _PC_ diff --git a/app/src/main/cpp/pcsx2/R5900.h b/app/src/main/cpp/pcsx2/R5900.h index de915bb..a2effc7 100644 --- a/app/src/main/cpp/pcsx2/R5900.h +++ b/app/src/main/cpp/pcsx2/R5900.h @@ -3,7 +3,7 @@ #pragma once -#include "cpuRegistersPack.h" +#include "arm64/VixlHelpers.h" #include // -------------------------------------------------------------------------------------- diff --git a/app/src/main/cpp/pcsx2/VUDef.h b/app/src/main/cpp/pcsx2/VUDef.h index b1e5f00..4e3fc11 100644 --- a/app/src/main/cpp/pcsx2/VUDef.h +++ b/app/src/main/cpp/pcsx2/VUDef.h @@ -257,6 +257,8 @@ struct mVU_SSE4 u32 g_minvals[4] = {0xff7fffff, 0xff7fffff, 0xff7fffff, 0xff7fffff}; u32 g_maxvals[4] = {0x7f7fffff, 0x7f7fffff, 0x7f7fffff, 0x7f7fffff}; //// + u32 result[4] = { 0x3f490fda }; + //// u32 minmax_mask[8] = { 0xffffffff, 0x80000000, 0, 0, diff --git a/app/src/main/cpp/pcsx2/arm64/ShuffleLanes.h b/app/src/main/cpp/pcsx2/arm64/ShuffleLanes.h new file mode 100644 index 0000000..847deb3 --- /dev/null +++ b/app/src/main/cpp/pcsx2/arm64/ShuffleLanes.h @@ -0,0 +1,272 @@ +// +// Created by k2154 on 2025-08-20. +// + +#ifndef PCSX2_SHUFFLELANES_H +#define PCSX2_SHUFFLELANES_H + +#include + +struct ShuffleLanes +{ + __uint8_t data[256][2][16] = { + {{0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3},{0, 1, 2, 3, 0, 1, 2, 3, 16, 17, 18, 19, 16, 17, 18, 19}}, + {{4, 5, 6, 7, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3},{4, 5, 6, 7, 0, 1, 2, 3, 16, 17, 18, 19, 16, 17, 18, 19}}, + {{8, 9, 10, 11, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3},{8, 9, 10, 11, 0, 1, 2, 3, 16, 17, 18, 19, 16, 17, 18, 19}}, + {{12, 13, 14, 15, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3},{12, 13, 14, 15, 0, 1, 2, 3, 16, 17, 18, 19, 16, 17, 18, 19}}, + {{0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 0, 1, 2, 3},{0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 16, 17, 18, 19}}, + {{4, 5, 6, 7, 4, 5, 6, 7, 0, 1, 2, 3, 0, 1, 2, 3},{4, 5, 6, 7, 4, 5, 6, 7, 16, 17, 18, 19, 16, 17, 18, 19}}, + {{8, 9, 10, 11, 4, 5, 6, 7, 0, 1, 2, 3, 0, 1, 2, 3},{8, 9, 10, 11, 4, 5, 6, 7, 16, 17, 18, 19, 16, 17, 18, 19}}, + {{12, 13, 14, 15, 4, 5, 6, 7, 0, 1, 2, 3, 0, 1, 2, 3},{12, 13, 14, 15, 4, 5, 6, 7, 16, 17, 18, 19, 16, 17, 18, 19}}, + {{0, 1, 2, 3, 8, 9, 10, 11, 0, 1, 2, 3, 0, 1, 2, 3},{0, 1, 2, 3, 8, 9, 10, 11, 16, 17, 18, 19, 16, 17, 18, 19}}, + {{4, 5, 6, 7, 8, 9, 10, 11, 0, 1, 2, 3, 0, 1, 2, 3},{4, 5, 6, 7, 8, 9, 10, 11, 16, 17, 18, 19, 16, 17, 18, 19}}, + {{8, 9, 10, 11, 8, 9, 10, 11, 0, 1, 2, 3, 0, 1, 2, 3},{8, 9, 10, 11, 8, 9, 10, 11, 16, 17, 18, 19, 16, 17, 18, 19}}, + {{12, 13, 14, 15, 8, 9, 10, 11, 0, 1, 2, 3, 0, 1, 2, 3},{12, 13, 14, 15, 8, 9, 10, 11, 16, 17, 18, 19, 16, 17, 18, 19}}, + {{0, 1, 2, 3, 12, 13, 14, 15, 0, 1, 2, 3, 0, 1, 2, 3},{0, 1, 2, 3, 12, 13, 14, 15, 16, 17, 18, 19, 16, 17, 18, 19}}, + {{4, 5, 6, 7, 12, 13, 14, 15, 0, 1, 2, 3, 0, 1, 2, 3},{4, 5, 6, 7, 12, 13, 14, 15, 16, 17, 18, 19, 16, 17, 18, 19}}, + {{8, 9, 10, 11, 12, 13, 14, 15, 0, 1, 2, 3, 0, 1, 2, 3},{8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 16, 17, 18, 19}}, + {{12, 13, 14, 15, 12, 13, 14, 15, 0, 1, 2, 3, 0, 1, 2, 3},{12, 13, 14, 15, 12, 13, 14, 15, 16, 17, 18, 19, 16, 17, 18, 19}}, + {{0, 1, 2, 3, 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3},{0, 1, 2, 3, 0, 1, 2, 3, 20, 21, 22, 23, 16, 17, 18, 19}}, + {{4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3},{4, 5, 6, 7, 0, 1, 2, 3, 20, 21, 22, 23, 16, 17, 18, 19}}, + {{8, 9, 10, 11, 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3},{8, 9, 10, 11, 0, 1, 2, 3, 20, 21, 22, 23, 16, 17, 18, 19}}, + {{12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3},{12, 13, 14, 15, 0, 1, 2, 3, 20, 21, 22, 23, 16, 17, 18, 19}}, + {{0, 1, 2, 3, 4, 5, 6, 7, 4, 5, 6, 7, 0, 1, 2, 3},{0, 1, 2, 3, 4, 5, 6, 7, 20, 21, 22, 23, 16, 17, 18, 19}}, + {{4, 5, 6, 7, 4, 5, 6, 7, 4, 5, 6, 7, 0, 1, 2, 3},{4, 5, 6, 7, 4, 5, 6, 7, 20, 21, 22, 23, 16, 17, 18, 19}}, + {{8, 9, 10, 11, 4, 5, 6, 7, 4, 5, 6, 7, 0, 1, 2, 3},{8, 9, 10, 11, 4, 5, 6, 7, 20, 21, 22, 23, 16, 17, 18, 19}}, + {{12, 13, 14, 15, 4, 5, 6, 7, 4, 5, 6, 7, 0, 1, 2, 3},{12, 13, 14, 15, 4, 5, 6, 7, 20, 21, 22, 23, 16, 17, 18, 19}}, + {{0, 1, 2, 3, 8, 9, 10, 11, 4, 5, 6, 7, 0, 1, 2, 3},{0, 1, 2, 3, 8, 9, 10, 11, 20, 21, 22, 23, 16, 17, 18, 19}}, + {{4, 5, 6, 7, 8, 9, 10, 11, 4, 5, 6, 7, 0, 1, 2, 3},{4, 5, 6, 7, 8, 9, 10, 11, 20, 21, 22, 23, 16, 17, 18, 19}}, + {{8, 9, 10, 11, 8, 9, 10, 11, 4, 5, 6, 7, 0, 1, 2, 3},{8, 9, 10, 11, 8, 9, 10, 11, 20, 21, 22, 23, 16, 17, 18, 19}}, + {{12, 13, 14, 15, 8, 9, 10, 11, 4, 5, 6, 7, 0, 1, 2, 3},{12, 13, 14, 15, 8, 9, 10, 11, 20, 21, 22, 23, 16, 17, 18, 19}}, + {{0, 1, 2, 3, 12, 13, 14, 15, 4, 5, 6, 7, 0, 1, 2, 3},{0, 1, 2, 3, 12, 13, 14, 15, 20, 21, 22, 23, 16, 17, 18, 19}}, + {{4, 5, 6, 7, 12, 13, 14, 15, 4, 5, 6, 7, 0, 1, 2, 3},{4, 5, 6, 7, 12, 13, 14, 15, 20, 21, 22, 23, 16, 17, 18, 19}}, + {{8, 9, 10, 11, 12, 13, 14, 15, 4, 5, 6, 7, 0, 1, 2, 3},{8, 9, 10, 11, 12, 13, 14, 15, 20, 21, 22, 23, 16, 17, 18, 19}}, + {{12, 13, 14, 15, 12, 13, 14, 15, 4, 5, 6, 7, 0, 1, 2, 3},{12, 13, 14, 15, 12, 13, 14, 15, 20, 21, 22, 23, 16, 17, 18, 19}}, + {{0, 1, 2, 3, 0, 1, 2, 3, 8, 9, 10, 11, 0, 1, 2, 3},{0, 1, 2, 3, 0, 1, 2, 3, 24, 25, 26, 27, 16, 17, 18, 19}}, + {{4, 5, 6, 7, 0, 1, 2, 3, 8, 9, 10, 11, 0, 1, 2, 3},{4, 5, 6, 7, 0, 1, 2, 3, 24, 25, 26, 27, 16, 17, 18, 19}}, + {{8, 9, 10, 11, 0, 1, 2, 3, 8, 9, 10, 11, 0, 1, 2, 3},{8, 9, 10, 11, 0, 1, 2, 3, 24, 25, 26, 27, 16, 17, 18, 19}}, + {{12, 13, 14, 15, 0, 1, 2, 3, 8, 9, 10, 11, 0, 1, 2, 3},{12, 13, 14, 15, 0, 1, 2, 3, 24, 25, 26, 27, 16, 17, 18, 19}}, + {{0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 0, 1, 2, 3},{0, 1, 2, 3, 4, 5, 6, 7, 24, 25, 26, 27, 16, 17, 18, 19}}, + {{4, 5, 6, 7, 4, 5, 6, 7, 8, 9, 10, 11, 0, 1, 2, 3},{4, 5, 6, 7, 4, 5, 6, 7, 24, 25, 26, 27, 16, 17, 18, 19}}, + {{8, 9, 10, 11, 4, 5, 6, 7, 8, 9, 10, 11, 0, 1, 2, 3},{8, 9, 10, 11, 4, 5, 6, 7, 24, 25, 26, 27, 16, 17, 18, 19}}, + {{12, 13, 14, 15, 4, 5, 6, 7, 8, 9, 10, 11, 0, 1, 2, 3},{12, 13, 14, 15, 4, 5, 6, 7, 24, 25, 26, 27, 16, 17, 18, 19}}, + {{0, 1, 2, 3, 8, 9, 10, 11, 8, 9, 10, 11, 0, 1, 2, 3},{0, 1, 2, 3, 8, 9, 10, 11, 24, 25, 26, 27, 16, 17, 18, 19}}, + {{4, 5, 6, 7, 8, 9, 10, 11, 8, 9, 10, 11, 0, 1, 2, 3},{4, 5, 6, 7, 8, 9, 10, 11, 24, 25, 26, 27, 16, 17, 18, 19}}, + {{8, 9, 10, 11, 8, 9, 10, 11, 8, 9, 10, 11, 0, 1, 2, 3},{8, 9, 10, 11, 8, 9, 10, 11, 24, 25, 26, 27, 16, 17, 18, 19}}, + {{12, 13, 14, 15, 8, 9, 10, 11, 8, 9, 10, 11, 0, 1, 2, 3},{12, 13, 14, 15, 8, 9, 10, 11, 24, 25, 26, 27, 16, 17, 18, 19}}, + {{0, 1, 2, 3, 12, 13, 14, 15, 8, 9, 10, 11, 0, 1, 2, 3},{0, 1, 2, 3, 12, 13, 14, 15, 24, 25, 26, 27, 16, 17, 18, 19}}, + {{4, 5, 6, 7, 12, 13, 14, 15, 8, 9, 10, 11, 0, 1, 2, 3},{4, 5, 6, 7, 12, 13, 14, 15, 24, 25, 26, 27, 16, 17, 18, 19}}, + {{8, 9, 10, 11, 12, 13, 14, 15, 8, 9, 10, 11, 0, 1, 2, 3},{8, 9, 10, 11, 12, 13, 14, 15, 24, 25, 26, 27, 16, 17, 18, 19}}, + {{12, 13, 14, 15, 12, 13, 14, 15, 8, 9, 10, 11, 0, 1, 2, 3},{12, 13, 14, 15, 12, 13, 14, 15, 24, 25, 26, 27, 16, 17, 18, 19}}, + {{0, 1, 2, 3, 0, 1, 2, 3, 12, 13, 14, 15, 0, 1, 2, 3},{0, 1, 2, 3, 0, 1, 2, 3, 28, 29, 30, 31, 16, 17, 18, 19}}, + {{4, 5, 6, 7, 0, 1, 2, 3, 12, 13, 14, 15, 0, 1, 2, 3},{4, 5, 6, 7, 0, 1, 2, 3, 28, 29, 30, 31, 16, 17, 18, 19}}, + {{8, 9, 10, 11, 0, 1, 2, 3, 12, 13, 14, 15, 0, 1, 2, 3},{8, 9, 10, 11, 0, 1, 2, 3, 28, 29, 30, 31, 16, 17, 18, 19}}, + {{12, 13, 14, 15, 0, 1, 2, 3, 12, 13, 14, 15, 0, 1, 2, 3},{12, 13, 14, 15, 0, 1, 2, 3, 28, 29, 30, 31, 16, 17, 18, 19}}, + {{0, 1, 2, 3, 4, 5, 6, 7, 12, 13, 14, 15, 0, 1, 2, 3},{0, 1, 2, 3, 4, 5, 6, 7, 28, 29, 30, 31, 16, 17, 18, 19}}, + {{4, 5, 6, 7, 4, 5, 6, 7, 12, 13, 14, 15, 0, 1, 2, 3},{4, 5, 6, 7, 4, 5, 6, 7, 28, 29, 30, 31, 16, 17, 18, 19}}, + {{8, 9, 10, 11, 4, 5, 6, 7, 12, 13, 14, 15, 0, 1, 2, 3},{8, 9, 10, 11, 4, 5, 6, 7, 28, 29, 30, 31, 16, 17, 18, 19}}, + {{12, 13, 14, 15, 4, 5, 6, 7, 12, 13, 14, 15, 0, 1, 2, 3},{12, 13, 14, 15, 4, 5, 6, 7, 28, 29, 30, 31, 16, 17, 18, 19}}, + {{0, 1, 2, 3, 8, 9, 10, 11, 12, 13, 14, 15, 0, 1, 2, 3},{0, 1, 2, 3, 8, 9, 10, 11, 28, 29, 30, 31, 16, 17, 18, 19}}, + {{4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 1, 2, 3},{4, 5, 6, 7, 8, 9, 10, 11, 28, 29, 30, 31, 16, 17, 18, 19}}, + {{8, 9, 10, 11, 8, 9, 10, 11, 12, 13, 14, 15, 0, 1, 2, 3},{8, 9, 10, 11, 8, 9, 10, 11, 28, 29, 30, 31, 16, 17, 18, 19}}, + {{12, 13, 14, 15, 8, 9, 10, 11, 12, 13, 14, 15, 0, 1, 2, 3},{12, 13, 14, 15, 8, 9, 10, 11, 28, 29, 30, 31, 16, 17, 18, 19}}, + {{0, 1, 2, 3, 12, 13, 14, 15, 12, 13, 14, 15, 0, 1, 2, 3},{0, 1, 2, 3, 12, 13, 14, 15, 28, 29, 30, 31, 16, 17, 18, 19}}, + {{4, 5, 6, 7, 12, 13, 14, 15, 12, 13, 14, 15, 0, 1, 2, 3},{4, 5, 6, 7, 12, 13, 14, 15, 28, 29, 30, 31, 16, 17, 18, 19}}, + {{8, 9, 10, 11, 12, 13, 14, 15, 12, 13, 14, 15, 0, 1, 2, 3},{8, 9, 10, 11, 12, 13, 14, 15, 28, 29, 30, 31, 16, 17, 18, 19}}, + {{12, 13, 14, 15, 12, 13, 14, 15, 12, 13, 14, 15, 0, 1, 2, 3},{12, 13, 14, 15, 12, 13, 14, 15, 28, 29, 30, 31, 16, 17, 18, 19}}, + {{0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 4, 5, 6, 7},{0, 1, 2, 3, 0, 1, 2, 3, 16, 17, 18, 19, 20, 21, 22, 23}}, + {{4, 5, 6, 7, 0, 1, 2, 3, 0, 1, 2, 3, 4, 5, 6, 7},{4, 5, 6, 7, 0, 1, 2, 3, 16, 17, 18, 19, 20, 21, 22, 23}}, + {{8, 9, 10, 11, 0, 1, 2, 3, 0, 1, 2, 3, 4, 5, 6, 7},{8, 9, 10, 11, 0, 1, 2, 3, 16, 17, 18, 19, 20, 21, 22, 23}}, + {{12, 13, 14, 15, 0, 1, 2, 3, 0, 1, 2, 3, 4, 5, 6, 7},{12, 13, 14, 15, 0, 1, 2, 3, 16, 17, 18, 19, 20, 21, 22, 23}}, + {{0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7},{0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 23}}, + {{4, 5, 6, 7, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7},{4, 5, 6, 7, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 23}}, + {{8, 9, 10, 11, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7},{8, 9, 10, 11, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 23}}, + {{12, 13, 14, 15, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7},{12, 13, 14, 15, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 23}}, + {{0, 1, 2, 3, 8, 9, 10, 11, 0, 1, 2, 3, 4, 5, 6, 7},{0, 1, 2, 3, 8, 9, 10, 11, 16, 17, 18, 19, 20, 21, 22, 23}}, + {{4, 5, 6, 7, 8, 9, 10, 11, 0, 1, 2, 3, 4, 5, 6, 7},{4, 5, 6, 7, 8, 9, 10, 11, 16, 17, 18, 19, 20, 21, 22, 23}}, + {{8, 9, 10, 11, 8, 9, 10, 11, 0, 1, 2, 3, 4, 5, 6, 7},{8, 9, 10, 11, 8, 9, 10, 11, 16, 17, 18, 19, 20, 21, 22, 23}}, + {{12, 13, 14, 15, 8, 9, 10, 11, 0, 1, 2, 3, 4, 5, 6, 7},{12, 13, 14, 15, 8, 9, 10, 11, 16, 17, 18, 19, 20, 21, 22, 23}}, + {{0, 1, 2, 3, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7},{0, 1, 2, 3, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23}}, + {{4, 5, 6, 7, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7},{4, 5, 6, 7, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23}}, + {{8, 9, 10, 11, 12, 13, 14, 15, 0, 1, 2, 3, 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9, 10, 11},{8, 9, 10, 11, 0, 1, 2, 3, 24, 25, 26, 27, 24, 25, 26, 27}}, + {{12, 13, 14, 15, 0, 1, 2, 3, 8, 9, 10, 11, 8, 9, 10, 11},{12, 13, 14, 15, 0, 1, 2, 3, 24, 25, 26, 27, 24, 25, 26, 27}}, + {{0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 8, 9, 10, 11},{0, 1, 2, 3, 4, 5, 6, 7, 24, 25, 26, 27, 24, 25, 26, 27}}, + {{4, 5, 6, 7, 4, 5, 6, 7, 8, 9, 10, 11, 8, 9, 10, 11},{4, 5, 6, 7, 4, 5, 6, 7, 24, 25, 26, 27, 24, 25, 26, 27}}, + {{8, 9, 10, 11, 4, 5, 6, 7, 8, 9, 10, 11, 8, 9, 10, 11},{8, 9, 10, 11, 4, 5, 6, 7, 24, 25, 26, 27, 24, 25, 26, 27}}, + {{12, 13, 14, 15, 4, 5, 6, 7, 8, 9, 10, 11, 8, 9, 10, 11},{12, 13, 14, 15, 4, 5, 6, 7, 24, 25, 26, 27, 24, 25, 26, 27}}, + {{0, 1, 2, 3, 8, 9, 10, 11, 8, 9, 10, 11, 8, 9, 10, 11},{0, 1, 2, 3, 8, 9, 10, 11, 24, 25, 26, 27, 24, 25, 26, 27}}, + {{4, 5, 6, 7, 8, 9, 10, 11, 8, 9, 10, 11, 8, 9, 10, 11},{4, 5, 6, 7, 8, 9, 10, 11, 24, 25, 26, 27, 24, 25, 26, 27}}, + {{8, 9, 10, 11, 8, 9, 10, 11, 8, 9, 10, 11, 8, 9, 10, 11},{8, 9, 10, 11, 8, 9, 10, 11, 24, 25, 26, 27, 24, 25, 26, 27}}, + {{12, 13, 14, 15, 8, 9, 10, 11, 8, 9, 10, 11, 8, 9, 10, 11},{12, 13, 14, 15, 8, 9, 10, 11, 24, 25, 26, 27, 24, 25, 26, 27}}, + {{0, 1, 2, 3, 12, 13, 14, 15, 8, 9, 10, 11, 8, 9, 10, 11},{0, 1, 2, 3, 12, 13, 14, 15, 24, 25, 26, 27, 24, 25, 26, 27}}, + {{4, 5, 6, 7, 12, 13, 14, 15, 8, 9, 10, 11, 8, 9, 10, 11},{4, 5, 6, 7, 12, 13, 14, 15, 24, 25, 26, 27, 24, 25, 26, 27}}, + {{8, 9, 10, 11, 12, 13, 14, 15, 8, 9, 10, 11, 8, 9, 10, 11},{8, 9, 10, 11, 12, 13, 14, 15, 24, 25, 26, 27, 24, 25, 26, 27}}, + {{12, 13, 14, 15, 12, 13, 14, 15, 8, 9, 10, 11, 8, 9, 10, 11},{12, 13, 14, 15, 12, 13, 14, 15, 24, 25, 26, 27, 24, 25, 26, 27}}, + {{0, 1, 2, 3, 0, 1, 2, 3, 12, 13, 14, 15, 8, 9, 10, 11},{0, 1, 2, 3, 0, 1, 2, 3, 28, 29, 30, 31, 24, 25, 26, 27}}, + {{4, 5, 6, 7, 0, 1, 2, 3, 12, 13, 14, 15, 8, 9, 10, 11},{4, 5, 6, 7, 0, 1, 2, 3, 28, 29, 30, 31, 24, 25, 26, 27}}, + {{8, 9, 10, 11, 0, 1, 2, 3, 12, 13, 14, 15, 8, 9, 10, 11},{8, 9, 10, 11, 0, 1, 2, 3, 28, 29, 30, 31, 24, 25, 26, 27}}, + {{12, 13, 14, 15, 0, 1, 2, 3, 12, 13, 14, 15, 8, 9, 10, 11},{12, 13, 14, 15, 0, 1, 2, 3, 28, 29, 30, 31, 24, 25, 26, 27}}, + {{0, 1, 2, 3, 4, 5, 6, 7, 12, 13, 14, 15, 8, 9, 10, 11},{0, 1, 2, 3, 4, 5, 6, 7, 28, 29, 30, 31, 24, 25, 26, 27}}, + {{4, 5, 6, 7, 4, 5, 6, 7, 12, 13, 14, 15, 8, 9, 10, 11},{4, 5, 6, 7, 4, 5, 6, 7, 28, 29, 30, 31, 24, 25, 26, 27}}, + {{8, 9, 10, 11, 4, 5, 6, 7, 12, 13, 14, 15, 8, 9, 10, 11},{8, 9, 10, 11, 4, 5, 6, 7, 28, 29, 30, 31, 24, 25, 26, 27}}, + {{12, 13, 14, 15, 4, 5, 6, 7, 12, 13, 14, 15, 8, 9, 10, 11},{12, 13, 14, 15, 4, 5, 6, 7, 28, 29, 30, 31, 24, 25, 26, 27}}, + {{0, 1, 2, 3, 8, 9, 10, 11, 12, 13, 14, 15, 8, 9, 10, 11},{0, 1, 2, 3, 8, 9, 10, 11, 28, 29, 30, 31, 24, 25, 26, 27}}, + {{4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 8, 9, 10, 11},{4, 5, 6, 7, 8, 9, 10, 11, 28, 29, 30, 31, 24, 25, 26, 27}}, + {{8, 9, 10, 11, 8, 9, 10, 11, 12, 13, 14, 15, 8, 9, 10, 11},{8, 9, 10, 11, 8, 9, 10, 11, 28, 29, 30, 31, 24, 25, 26, 27}}, + {{12, 13, 14, 15, 8, 9, 10, 11, 12, 13, 14, 15, 8, 9, 10, 11},{12, 13, 14, 15, 8, 9, 10, 11, 28, 29, 30, 31, 24, 25, 26, 27}}, + {{0, 1, 2, 3, 12, 13, 14, 15, 12, 13, 14, 15, 8, 9, 10, 11},{0, 1, 2, 3, 12, 13, 14, 15, 28, 29, 30, 31, 24, 25, 26, 27}}, + {{4, 5, 6, 7, 12, 13, 14, 15, 12, 13, 14, 15, 8, 9, 10, 11},{4, 5, 6, 7, 12, 13, 14, 15, 28, 29, 30, 31, 24, 25, 26, 27}}, + {{8, 9, 10, 11, 12, 13, 14, 15, 12, 13, 14, 15, 8, 9, 10, 11},{8, 9, 10, 11, 12, 13, 14, 15, 28, 29, 30, 31, 24, 25, 26, 27}}, + {{12, 13, 14, 15, 12, 13, 14, 15, 12, 13, 14, 15, 8, 9, 10, 11},{12, 13, 14, 15, 12, 13, 14, 15, 28, 29, 30, 31, 24, 25, 26, 27}}, + {{0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 12, 13, 14, 15},{0, 1, 2, 3, 0, 1, 2, 3, 16, 17, 18, 19, 28, 29, 30, 31}}, + {{4, 5, 6, 7, 0, 1, 2, 3, 0, 1, 2, 3, 12, 13, 14, 15},{4, 5, 6, 7, 0, 1, 2, 3, 16, 17, 18, 19, 28, 29, 30, 31}}, + {{8, 9, 10, 11, 0, 1, 2, 3, 0, 1, 2, 3, 12, 13, 14, 15},{8, 9, 10, 11, 0, 1, 2, 3, 16, 17, 18, 19, 28, 29, 30, 31}}, + {{12, 13, 14, 15, 0, 1, 2, 3, 0, 1, 2, 3, 12, 13, 14, 15},{12, 13, 14, 15, 0, 1, 2, 3, 16, 17, 18, 19, 28, 29, 30, 31}}, + {{0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 12, 13, 14, 15},{0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 28, 29, 30, 31}}, + {{4, 5, 6, 7, 4, 5, 6, 7, 0, 1, 2, 3, 12, 13, 14, 15},{4, 5, 6, 7, 4, 5, 6, 7, 16, 17, 18, 19, 28, 29, 30, 31}}, + {{8, 9, 10, 11, 4, 5, 6, 7, 0, 1, 2, 3, 12, 13, 14, 15},{8, 9, 10, 11, 4, 5, 6, 7, 16, 17, 18, 19, 28, 29, 30, 31}}, + {{12, 13, 14, 15, 4, 5, 6, 7, 0, 1, 2, 3, 12, 13, 14, 15},{12, 13, 14, 15, 4, 5, 6, 7, 16, 17, 18, 19, 28, 29, 30, 31}}, + {{0, 1, 2, 3, 8, 9, 10, 11, 0, 1, 2, 3, 12, 13, 14, 15},{0, 1, 2, 3, 8, 9, 10, 11, 16, 17, 18, 19, 28, 29, 30, 31}}, + {{4, 5, 6, 7, 8, 9, 10, 11, 0, 1, 2, 3, 12, 13, 14, 15},{4, 5, 6, 7, 8, 9, 10, 11, 16, 17, 18, 19, 28, 29, 30, 31}}, + {{8, 9, 10, 11, 8, 9, 10, 11, 0, 1, 2, 3, 12, 13, 14, 15},{8, 9, 10, 11, 8, 9, 10, 11, 16, 17, 18, 19, 28, 29, 30, 31}}, + {{12, 13, 14, 15, 8, 9, 10, 11, 0, 1, 2, 3, 12, 13, 14, 15},{12, 13, 14, 15, 8, 9, 10, 11, 16, 17, 18, 19, 28, 29, 30, 31}}, + {{0, 1, 2, 3, 12, 13, 14, 15, 0, 1, 2, 3, 12, 13, 14, 15},{0, 1, 2, 3, 12, 13, 14, 15, 16, 17, 18, 19, 28, 29, 30, 31}}, + {{4, 5, 6, 7, 12, 13, 14, 15, 0, 1, 2, 3, 12, 13, 14, 15},{4, 5, 6, 7, 12, 13, 14, 15, 16, 17, 18, 19, 28, 29, 30, 31}}, + {{8, 9, 10, 11, 12, 13, 14, 15, 0, 1, 2, 3, 12, 13, 14, 15},{8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 28, 29, 30, 31}}, + {{12, 13, 14, 15, 12, 13, 14, 15, 0, 1, 2, 3, 12, 13, 14, 15},{12, 13, 14, 15, 12, 13, 14, 15, 16, 17, 18, 19, 28, 29, 30, 31}}, + {{0, 1, 2, 3, 0, 1, 2, 3, 4, 5, 6, 7, 12, 13, 14, 15},{0, 1, 2, 3, 0, 1, 2, 3, 20, 21, 22, 23, 28, 29, 30, 31}}, + {{4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7, 12, 13, 14, 15},{4, 5, 6, 7, 0, 1, 2, 3, 20, 21, 22, 23, 28, 29, 30, 31}}, + {{8, 9, 10, 11, 0, 1, 2, 3, 4, 5, 6, 7, 12, 13, 14, 15},{8, 9, 10, 11, 0, 1, 2, 3, 20, 21, 22, 23, 28, 29, 30, 31}}, + {{12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 12, 13, 14, 15},{12, 13, 14, 15, 0, 1, 2, 3, 20, 21, 22, 23, 28, 29, 30, 31}}, + {{0, 1, 2, 3, 4, 5, 6, 7, 4, 5, 6, 7, 12, 13, 14, 15},{0, 1, 2, 3, 4, 5, 6, 7, 20, 21, 22, 23, 28, 29, 30, 31}}, + {{4, 5, 6, 7, 4, 5, 6, 7, 4, 5, 6, 7, 12, 13, 14, 15},{4, 5, 6, 7, 4, 5, 6, 7, 20, 21, 22, 23, 28, 29, 30, 31}}, + {{8, 9, 10, 11, 4, 5, 6, 7, 4, 5, 6, 7, 12, 13, 14, 15},{8, 9, 10, 11, 4, 5, 6, 7, 20, 21, 22, 23, 28, 29, 30, 31}}, + {{12, 13, 14, 15, 4, 5, 6, 7, 4, 5, 6, 7, 12, 13, 14, 15},{12, 13, 14, 15, 4, 5, 6, 7, 20, 21, 22, 23, 28, 29, 30, 31}}, + {{0, 1, 2, 3, 8, 9, 10, 11, 4, 5, 6, 7, 12, 13, 14, 15},{0, 1, 2, 3, 8, 9, 10, 11, 20, 21, 22, 23, 28, 29, 30, 31}}, + {{4, 5, 6, 7, 8, 9, 10, 11, 4, 5, 6, 7, 12, 13, 14, 15},{4, 5, 6, 7, 8, 9, 10, 11, 20, 21, 22, 23, 28, 29, 30, 31}}, + {{8, 9, 10, 11, 8, 9, 10, 11, 4, 5, 6, 7, 12, 13, 14, 15},{8, 9, 10, 11, 8, 9, 10, 11, 20, 21, 22, 23, 28, 29, 30, 31}}, + {{12, 13, 14, 15, 8, 9, 10, 11, 4, 5, 6, 7, 12, 13, 14, 15},{12, 13, 14, 15, 8, 9, 10, 11, 20, 21, 22, 23, 28, 29, 30, 31}}, + {{0, 1, 2, 3, 12, 13, 14, 15, 4, 5, 6, 7, 12, 13, 14, 15},{0, 1, 2, 3, 12, 13, 14, 15, 20, 21, 22, 23, 28, 29, 30, 31}}, + {{4, 5, 6, 7, 12, 13, 14, 15, 4, 5, 6, 7, 12, 13, 14, 15},{4, 5, 6, 7, 12, 13, 14, 15, 20, 21, 22, 23, 28, 29, 30, 31}}, + {{8, 9, 10, 11, 12, 13, 14, 15, 4, 5, 6, 7, 12, 13, 14, 15},{8, 9, 10, 11, 12, 13, 14, 15, 20, 21, 22, 23, 28, 29, 30, 31}}, + {{12, 13, 14, 15, 12, 13, 14, 15, 4, 5, 6, 7, 12, 13, 14, 15},{12, 13, 14, 15, 12, 13, 14, 15, 20, 21, 22, 23, 28, 29, 30, 31}}, + {{0, 1, 2, 3, 0, 1, 2, 3, 8, 9, 10, 11, 12, 13, 14, 15},{0, 1, 2, 3, 0, 1, 2, 3, 24, 25, 26, 27, 28, 29, 30, 31}}, + {{4, 5, 6, 7, 0, 1, 2, 3, 8, 9, 10, 11, 12, 13, 14, 15},{4, 5, 6, 7, 0, 1, 2, 3, 24, 25, 26, 27, 28, 29, 30, 31}}, + {{8, 9, 10, 11, 0, 1, 2, 3, 8, 9, 10, 11, 12, 13, 14, 15},{8, 9, 10, 11, 0, 1, 2, 3, 24, 25, 26, 27, 28, 29, 30, 31}}, + {{12, 13, 14, 15, 0, 1, 2, 3, 8, 9, 10, 11, 12, 13, 14, 15},{12, 13, 14, 15, 0, 1, 2, 3, 24, 25, 26, 27, 28, 29, 30, 31}}, + {{0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15},{0, 1, 2, 3, 4, 5, 6, 7, 24, 25, 26, 27, 28, 29, 30, 31}}, + {{4, 5, 6, 7, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15},{4, 5, 6, 7, 4, 5, 6, 7, 24, 25, 26, 27, 28, 29, 30, 31}}, + {{8, 9, 10, 11, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15},{8, 9, 10, 11, 4, 5, 6, 7, 24, 25, 26, 27, 28, 29, 30, 31}}, + {{12, 13, 14, 15, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15},{12, 13, 14, 15, 4, 5, 6, 7, 24, 25, 26, 27, 28, 29, 30, 31}}, + {{0, 1, 2, 3, 8, 9, 10, 11, 8, 9, 10, 11, 12, 13, 14, 15},{0, 1, 2, 3, 8, 9, 10, 11, 24, 25, 26, 27, 28, 29, 30, 31}}, + {{4, 5, 6, 7, 8, 9, 10, 11, 8, 9, 10, 11, 12, 13, 14, 15},{4, 5, 6, 7, 8, 9, 10, 11, 24, 25, 26, 27, 28, 29, 30, 31}}, + {{8, 9, 10, 11, 8, 9, 10, 11, 8, 9, 10, 11, 12, 13, 14, 15},{8, 9, 10, 11, 8, 9, 10, 11, 24, 25, 26, 27, 28, 29, 30, 31}}, + {{12, 13, 14, 15, 8, 9, 10, 11, 8, 9, 10, 11, 12, 13, 14, 15},{12, 13, 14, 15, 8, 9, 10, 11, 24, 25, 26, 27, 28, 29, 30, 31}}, + {{0, 1, 2, 3, 12, 13, 14, 15, 8, 9, 10, 11, 12, 13, 14, 15},{0, 1, 2, 3, 12, 13, 14, 15, 24, 25, 26, 27, 28, 29, 30, 31}}, + {{4, 5, 6, 7, 12, 13, 14, 15, 8, 9, 10, 11, 12, 13, 14, 15},{4, 5, 6, 7, 12, 13, 14, 15, 24, 25, 26, 27, 28, 29, 30, 31}}, + {{8, 9, 10, 11, 12, 13, 14, 15, 8, 9, 10, 11, 12, 13, 14, 15},{8, 9, 10, 11, 12, 13, 14, 15, 24, 25, 26, 27, 28, 29, 30, 31}}, + {{12, 13, 14, 15, 12, 13, 14, 15, 8, 9, 10, 11, 12, 13, 14, 15},{12, 13, 14, 15, 12, 13, 14, 15, 24, 25, 26, 27, 28, 29, 30, 31}}, + {{0, 1, 2, 3, 0, 1, 2, 3, 12, 13, 14, 15, 12, 13, 14, 15},{0, 1, 2, 3, 0, 1, 2, 3, 28, 29, 30, 31, 28, 29, 30, 31}}, + {{4, 5, 6, 7, 0, 1, 2, 3, 12, 13, 14, 15, 12, 13, 14, 15},{4, 5, 6, 7, 0, 1, 2, 3, 28, 29, 30, 31, 28, 29, 30, 31}}, + {{8, 9, 10, 11, 0, 1, 2, 3, 12, 13, 14, 15, 12, 13, 14, 15},{8, 9, 10, 11, 0, 1, 2, 3, 28, 29, 30, 31, 28, 29, 30, 31}}, + {{12, 13, 14, 15, 0, 1, 2, 3, 12, 13, 14, 15, 12, 13, 14, 15},{12, 13, 14, 15, 0, 1, 2, 3, 28, 29, 30, 31, 28, 29, 30, 31}}, + {{0, 1, 2, 3, 4, 5, 6, 7, 12, 13, 14, 15, 12, 13, 14, 15},{0, 1, 2, 3, 4, 5, 6, 7, 28, 29, 30, 31, 28, 29, 30, 31}}, + {{4, 5, 6, 7, 4, 5, 6, 7, 12, 13, 14, 15, 12, 13, 14, 15},{4, 5, 6, 7, 4, 5, 6, 7, 28, 29, 30, 31, 28, 29, 30, 31}}, + {{8, 9, 10, 11, 4, 5, 6, 7, 12, 13, 14, 15, 12, 13, 14, 15},{8, 9, 10, 11, 4, 5, 6, 7, 28, 29, 30, 31, 28, 29, 30, 31}}, + {{12, 13, 14, 15, 4, 5, 6, 7, 12, 13, 14, 15, 12, 13, 14, 15},{12, 13, 14, 15, 4, 5, 6, 7, 28, 29, 30, 31, 28, 29, 30, 31}}, + {{0, 1, 2, 3, 8, 9, 10, 11, 12, 13, 14, 15, 12, 13, 14, 15},{0, 1, 2, 3, 8, 9, 10, 11, 28, 29, 30, 31, 28, 29, 30, 31}}, + {{4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 12, 13, 14, 15},{4, 5, 6, 7, 8, 9, 10, 11, 28, 29, 30, 31, 28, 29, 30, 31}}, + {{8, 9, 10, 11, 8, 9, 10, 11, 12, 13, 14, 15, 12, 13, 14, 15},{8, 9, 10, 11, 8, 9, 10, 11, 28, 29, 30, 31, 28, 29, 30, 31}}, + {{12, 13, 14, 15, 8, 9, 10, 11, 12, 13, 14, 15, 12, 13, 14, 15},{12, 13, 14, 15, 8, 9, 10, 11, 28, 29, 30, 31, 28, 29, 30, 31}}, + {{0, 1, 2, 3, 12, 13, 14, 15, 12, 13, 14, 15, 12, 13, 14, 15},{0, 1, 2, 3, 12, 13, 14, 15, 28, 29, 30, 31, 28, 29, 30, 31}}, + {{4, 5, 6, 7, 12, 13, 14, 15, 12, 13, 14, 15, 12, 13, 14, 15},{4, 5, 6, 7, 12, 13, 14, 15, 28, 29, 30, 31, 28, 29, 30, 31}}, + {{8, 9, 10, 11, 12, 13, 14, 15, 12, 13, 14, 15, 12, 13, 14, 15},{8, 9, 10, 11, 12, 13, 14, 15, 28, 29, 30, 31, 28, 29, 30, 31}}, + {{12, 13, 14, 15, 12, 13, 14, 15, 12, 13, 14, 15, 12, 13, 14, 15},{12, 13, 14, 15, 12, 13, 14, 15, 28, 29, 30, 31, 28, 29, 30, 31}} + }; +}; + +#endif //PCSX2_SHUFFLELANES_H diff --git a/app/src/main/cpp/pcsx2/arm64/Vif_UnpackNEON.h b/app/src/main/cpp/pcsx2/arm64/Vif_UnpackNEON.h index 43c77d2..0ff47c8 100644 --- a/app/src/main/cpp/pcsx2/arm64/Vif_UnpackNEON.h +++ b/app/src/main/cpp/pcsx2/arm64/Vif_UnpackNEON.h @@ -6,7 +6,7 @@ #include "Common.h" #include "Vif_Dma.h" #include "Vif_Dynarec.h" -#include "common/arm64/AsmHelpers.h" +#include "VixlHelpers.h" #define xmmCol0 vixl::aarch64::q2 #define xmmCol1 vixl::aarch64::q3 diff --git a/app/src/main/cpp/common/arm64/AsmHelpers.cpp b/app/src/main/cpp/pcsx2/arm64/VixlHelpers.cpp similarity index 94% rename from app/src/main/cpp/common/arm64/AsmHelpers.cpp rename to app/src/main/cpp/pcsx2/arm64/VixlHelpers.cpp index c756f23..1798667 100644 --- a/app/src/main/cpp/common/arm64/AsmHelpers.cpp +++ b/app/src/main/cpp/pcsx2/arm64/VixlHelpers.cpp @@ -1,7 +1,7 @@ // SPDX-FileCopyrightText: 2002-2024 PCSX2 Dev Team // SPDX-License-Identifier: GPL-3.0 -#include "common/arm64/AsmHelpers.h" +#include "VixlHelpers.h" #include "common/Assertions.h" #include "common/BitUtils.h" @@ -160,7 +160,8 @@ void armEmitJmp(const void* ptr, bool force_inline) if (use_blr) { - armAsm->Mov(RXVIXLSCRATCH, reinterpret_cast(ptr)); + armAsm->Mov(RXVIXLSCRATCH, (uptr)ptr); +// armAsm->Ldr(RXVIXLSCRATCH, (uptr)ptr); armAsm->Br(RXVIXLSCRATCH); } else @@ -185,7 +186,8 @@ void armEmitCall(const void* ptr, bool force_inline) if (use_blr) { - armAsm->Mov(RXVIXLSCRATCH, reinterpret_cast(ptr)); + armAsm->Mov(RXVIXLSCRATCH, (uptr)ptr); +// armAsm->Ldr(RXVIXLSCRATCH, (uptr)ptr); armAsm->Blr(RXVIXLSCRATCH); } else @@ -275,6 +277,16 @@ void armMoveAddressToReg(const a64::Register& reg, const void* addr) } } +void armCbz(const a64::Register& reg, a64::Label* p_label) +{ + armAsm->Cbz(reg, p_label); +} + +void armCbnz(const a64::Register& reg, a64::Label* p_label) +{ + armAsm->Cbnz(reg, p_label); +} + void armLoadPtr(const a64::CPURegister& reg, const void* addr) { armMoveAddressToReg(RSCRATCHADDR, addr); @@ -997,67 +1009,17 @@ void armPMOVMSKB(const a64::Register& regDst, const a64::VRegister& regSrc) void armSHUFPS(const a64::VRegister& dstreg, const a64::VRegister& srcreg, int pIndex) { - armShuffle(dstreg, srcreg, pIndex, true); + armAsm->Mov(RQSCRATCH3, armLoadPtrV(PTR_CPU(shuffle.data[pIndex][1])).Q()); + //// + armAsm->Mov(RQSCRATCH2, srcreg); + armAsm->Mov(RQSCRATCH, dstreg); + armAsm->Tbx(dstreg.V16B(), RQSCRATCH.V16B(), RQSCRATCH2.V16B(), RQSCRATCH3.V16B()); } void armPSHUFD(const a64::VRegister& dstreg, const a64::VRegister& srcreg, int pIndex) { - armShuffle(dstreg, srcreg, pIndex, false); -} - -void armShuffleTblx(const a64::VRegister& p_dst, const a64::VRegister& p_src, int p_a, int p_b, int p_c, int p_d, bool p_is_tbx) -{ - uint8_t lanes[16]; - int i, s, e, nIndex = 0; - - int lanesTbx = 0; - if(p_is_tbx) { - lanesTbx = 16; - } - - // 0, 4, 8, 12 - // 0 * 4 = 0, 1 * 4 = 4, 2 * 4 = 8, 3 * 4 = 12 - // lanes 16 => 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 - - s = p_a << 2; e = s + 4; - for(i=s; iMov(RQSCRATCH, p_dst); - armAsm->Mov(RQSCRATCH2, p_src); - armAsm->Tbx(p_dst.V16B(), RQSCRATCH.V16B(), RQSCRATCH2.V16B(), RQSCRATCH3.V16B()); - } else { - armAsm->Tbl(p_dst.V16B(), p_src.V16B(), RQSCRATCH3.V16B()); - } -} - -void armShuffle(const a64::VRegister& dstreg, const a64::VRegister& srcreg, int pIndex, bool p_is_tbx) -{ - int shuffle_0 = (pIndex >> 0) & 0x3; - int shuffle_1 = (pIndex >> 2) & 0x3; - int shuffle_2 = (pIndex >> 4) & 0x3; - int shuffle_3 = (pIndex >> 6) & 0x3; - //// - armShuffleTblx(dstreg, srcreg, shuffle_0, shuffle_1, shuffle_2, shuffle_3, p_is_tbx); + armAsm->Mov(RQSCRATCH3, armLoadPtrV(PTR_CPU(shuffle.data[pIndex][0])).Q()); + armAsm->Tbl(dstreg.V16B(), srcreg.V16B(), RQSCRATCH3.V16B()); } int find_bit_pos(uint32_t p_hex_value) diff --git a/app/src/main/cpp/common/arm64/AsmHelpers.h b/app/src/main/cpp/pcsx2/arm64/VixlHelpers.h similarity index 97% rename from app/src/main/cpp/common/arm64/AsmHelpers.h rename to app/src/main/cpp/pcsx2/arm64/VixlHelpers.h index d027345..baa5d6d 100644 --- a/app/src/main/cpp/common/arm64/AsmHelpers.h +++ b/app/src/main/cpp/pcsx2/arm64/VixlHelpers.h @@ -3,14 +3,14 @@ #pragma once +#include #include "common/Pcsx2Defs.h" #include "common/HashCombine.h" +#include "cpuRegistersPack.h" #include "vixl/aarch64/constants-aarch64.h" #include "vixl/aarch64/macro-assembler-aarch64.h" -#include - namespace a64 = vixl::aarch64; #define RWARG1 a64::w0 @@ -72,6 +72,9 @@ namespace a64 = vixl::aarch64; // iopMem->Main #define RSTATE_x29 a64::x29 +// eeHw[Ps2MemSize::Hardware] +#define psHu(mem) (mem & 0xffff) + static inline s64 GetPCDisplacement(const void* current, const void* target) { return static_cast((reinterpret_cast(target) - reinterpret_cast(current)) >> 2); @@ -118,6 +121,8 @@ void armEmitCall(const void* ptr, bool force_inline = false); void armEmitCbnz(const a64::Register& reg, const void* ptr); void armEmitCondBranch(a64::Condition cond, const void* ptr); void armMoveAddressToReg(const a64::Register& reg, const void* addr); +void armCbz(const a64::Register& reg, a64::Label* p_label); +void armCbnz(const a64::Register& reg, a64::Label* p_label); void armLoadPtr(const a64::CPURegister& reg, const void* addr); void armStorePtr(const a64::CPURegister& reg, const void* addr); void armBeginStackFrame(bool save_fpr=true); @@ -252,7 +257,6 @@ void armPMOVMSKB(const a64::Register& regDst, const a64::VRegister& regSrc); void armSHUFPS(const a64::VRegister& dstreg, const a64::VRegister& srcreg, int pIndex); void armPSHUFD(const a64::VRegister& dstreg, const a64::VRegister& srcreg, int pIndex); -void armShuffleTblx(const a64::VRegister& p_dst, const a64::VRegister& p_src, int p_a, int p_b, int p_c, int p_d, bool p_is_tbx); -void armShuffle(const a64::VRegister& dstreg, const a64::VRegister& srcreg, int pIndex, bool p_is_tbx); +void armShuffleTblx(const a64::VRegister& p_dst, const a64::VRegister& p_src, int pIndex, bool p_is_tbx); int find_bit_pos(uint32_t p_hex_value); diff --git a/app/src/main/cpp/pcsx2/cpuRegistersPack.h b/app/src/main/cpp/pcsx2/arm64/cpuRegistersPack.h similarity index 87% rename from app/src/main/cpp/pcsx2/cpuRegistersPack.h rename to app/src/main/cpp/pcsx2/arm64/cpuRegistersPack.h index d4450a3..7c0c4a4 100644 --- a/app/src/main/cpp/pcsx2/cpuRegistersPack.h +++ b/app/src/main/cpp/pcsx2/arm64/cpuRegistersPack.h @@ -5,10 +5,12 @@ #ifndef PCSX2_CPUREGISTERSPACK_H #define PCSX2_CPUREGISTERSPACK_H +#include "Config.h" #include "R5900Def.h" #include "R3000ADef.h" #include "VUDef.h" #include "vtlbDef.h" +#include "arm64/ShuffleLanes.h" struct cpuRegistersPack { @@ -17,6 +19,8 @@ struct cpuRegistersPack alignas(16) psxRegisters psxRegs{}; alignas(16) VIFregisters vifRegs[2]{}; alignas(16) VURegs vuRegs[2]; + alignas(16) ShuffleLanes shuffle; + alignas(16) Pcsx2Config::CpuOptions Cpu; alignas(16) mVU_SSE4 mVUss4; alignas(32) mVU_Globals mVUglob; alignas(64) vtlb_private::MapData vtlbdata; diff --git a/app/src/main/cpp/pcsx2/vtlbDef.h b/app/src/main/cpp/pcsx2/vtlbDef.h index 5bd75a3..0eeb71c 100644 --- a/app/src/main/cpp/pcsx2/vtlbDef.h +++ b/app/src/main/cpp/pcsx2/vtlbDef.h @@ -77,7 +77,7 @@ namespace vtlb_private struct VTLBVirtual { - public: + private: uptr value; explicit VTLBVirtual(uptr value): value(value) { } public: diff --git a/app/src/main/cpp/pcsx2/x86/BaseblockEx.h b/app/src/main/cpp/pcsx2/x86/BaseblockEx.h index 396a4de..002ae6f 100644 --- a/app/src/main/cpp/pcsx2/x86/BaseblockEx.h +++ b/app/src/main/cpp/pcsx2/x86/BaseblockEx.h @@ -7,7 +7,7 @@ #include #include "common/Assertions.h" -#include "common/arm64/AsmHelpers.h" +#include "arm64/VixlHelpers.h" // Every potential jump point in the PS2's addressable memory has a BASEBLOCK // associated with it. So that means a BASEBLOCK for every 4 bytes of PS2 diff --git a/app/src/main/cpp/pcsx2/x86/iCOP0.cpp b/app/src/main/cpp/pcsx2/x86/iCOP0.cpp index 525d12a..0f5b532 100644 --- a/app/src/main/cpp/pcsx2/x86/iCOP0.cpp +++ b/app/src/main/cpp/pcsx2/x86/iCOP0.cpp @@ -42,13 +42,15 @@ static void _setupBranchTest() // everything except the lower 10 bits away. // xMOV(eax, ptr[(&psHu32(DMAC_PCR))]); - armAsm->Ldr(EAX, armMemOperandPtr(&psHu32(DMAC_PCR))); + armAsm->Ldr(RXVIXLSCRATCH, a64::MemOperand(RSTATE_x26, psHu(DMAC_PCR))); + armAsm->Uxtw(EAX, RXVIXLSCRATCH); // xMOV(ecx, 0x3ff); // ECX is our 10-bit mask var armAsm->Mov(ECX, 0x3ff); // xNOT(eax); armAsm->Mvn(EAX, EAX); // xOR(eax, ptr[(&psHu32(DMAC_STAT))]); - armAsm->Orr(EAX, EAX, armLoadPtr((&psHu32(DMAC_STAT)))); + armAsm->Ldr(RXVIXLSCRATCH, a64::MemOperand(RSTATE_x26, psHu(DMAC_STAT))); + armAsm->Orr(EAX, EAX, a64::Operand(RXVIXLSCRATCH, a64::Extend::UXTW)); // xAND(eax, ecx); armAsm->And(EAX, EAX, ECX); // xCMP(eax, ecx); diff --git a/app/src/main/cpp/pcsx2/x86/iFPU.cpp b/app/src/main/cpp/pcsx2/x86/iFPU.cpp index 686d22c..bf2a132 100644 --- a/app/src/main/cpp/pcsx2/x86/iFPU.cpp +++ b/app/src/main/cpp/pcsx2/x86/iFPU.cpp @@ -651,7 +651,7 @@ void FPU_MUL(int regd, int regt, bool reverseOperands) // else // return 0; - alignas(16) static constexpr const u32 result[4] = { 0x3f490fda }; +// alignas(16) static constexpr const u32 result[4] = { 0x3f490fda }; // xMOVD(ecx, xRegisterSSE(reverseOperands ? regt : regd)); armAsm->Fmov(ECX, reverseOperands ? regT.S() : regD.S()); @@ -668,9 +668,9 @@ void FPU_MUL(int regd, int regt, bool reverseOperands) // u8* noHack = JNZ8(0); a64::Label noHack; - armAsm->Cbnz(EDX, &noHack); + armCbnz(EDX, &noHack); // xMOVAPS(xRegisterSSE(regd), ptr128[result]); - armAsm->Ldr(regD.Q(), armMemOperandPtr(result)); + armAsm->Ldr(regD.Q(), PTR_CPU(mVUss4.result)); // endMul = JMP8(0); armAsm->B(&endMul); // x86SetJ8(noHack); @@ -1414,7 +1414,7 @@ void recDIV_S_xmm(int info) if (EmuConfig.Cpu.FPUFPCR.bitmask != EmuConfig.Cpu.FPUDivFPCR.bitmask) { // xLDMXCSR(ptr32[&EmuConfig.Cpu.FPUDivFPCR.bitmask]); - armAsm->Msr(a64::FPCR, armLoadPtr64(&EmuConfig.Cpu.FPUDivFPCR.bitmask)); + armAsm->Msr(a64::FPCR, armLoad64(PTR_CPU(Cpu.FPUDivFPCR.bitmask))); } switch (info & (PROCESS_EE_S | PROCESS_EE_T)) @@ -1491,7 +1491,7 @@ void recDIV_S_xmm(int info) if (EmuConfig.Cpu.FPUFPCR.bitmask != EmuConfig.Cpu.FPUDivFPCR.bitmask) { // xLDMXCSR(ptr32[&EmuConfig.Cpu.FPUFPCR.bitmask]); - armAsm->Msr(a64::FPCR, armLoadPtr64(&EmuConfig.Cpu.FPUFPCR.bitmask)); + armAsm->Msr(a64::FPCR, armLoad64(PTR_CPU(Cpu.FPUFPCR.bitmask))); } _freeXMMreg(t0reg); @@ -2213,7 +2213,7 @@ void recSQRT_S_xmm(int info) roundmode_nearest = EmuConfig.Cpu.FPUFPCR; roundmode_nearest.SetRoundMode(FPRoundMode::Nearest); // xLDMXCSR(ptr32[&roundmode_nearest.bitmask]); - armAsm->Msr(a64::FPCR, armLoadPtr64(&roundmode_nearest.bitmask)); + armAsm->Msr(a64::FPCR, armLoad64(PTR_CPU(Cpu.FPUFPCR.bitmask))); roundmodeFlag = true; } @@ -2262,7 +2262,7 @@ void recSQRT_S_xmm(int info) if (roundmodeFlag) { // xLDMXCSR(ptr32[&EmuConfig.Cpu.FPUFPCR.bitmask]); - armAsm->Msr(a64::FPCR, armLoadPtr64(&EmuConfig.Cpu.FPUFPCR.bitmask)); + armAsm->Msr(a64::FPCR, armLoad64(PTR_CPU(Cpu.FPUFPCR.bitmask))); } } diff --git a/app/src/main/cpp/pcsx2/x86/iFPUd.cpp b/app/src/main/cpp/pcsx2/x86/iFPUd.cpp index da32857..0506f5f 100644 --- a/app/src/main/cpp/pcsx2/x86/iFPUd.cpp +++ b/app/src/main/cpp/pcsx2/x86/iFPUd.cpp @@ -545,7 +545,7 @@ void FPU_MUL(int info, int regd, int sreg, int treg, bool acc) // else // return 0; - alignas(16) static constexpr const u32 result[4] = { 0x3f490fda }; +// alignas(16) static constexpr const u32 result[4] = { 0x3f490fda }; // xMOVD(ecx, xRegisterSSE(sreg)); armAsm->Fmov(ECX, regS.S()); @@ -562,9 +562,9 @@ void FPU_MUL(int info, int regd, int sreg, int treg, bool acc) // u8* noHack = JNZ8(0); a64::Label noHack; - armAsm->Cbnz(EDX, &noHack); + armCbnz(EDX, &noHack); // xMOVAPS(xRegisterSSE(regd), ptr128[result]); - armAsm->Ldr(regD.Q(), armMemOperandPtr(result)); + armAsm->Ldr(regD.Q(), PTR_CPU(mVUss4.result)); // endMul = JMP32(0); armAsm->B(&endMul); // x86SetJ8(noHack); @@ -835,7 +835,7 @@ void recDIV_S_xmm(int info) if (EmuConfig.Cpu.FPUFPCR.bitmask != EmuConfig.Cpu.FPUDivFPCR.bitmask) { // xLDMXCSR(ptr32[&EmuConfig.Cpu.FPUDivFPCR.bitmask]); - armAsm->Msr(a64::FPCR, armLoadPtr64(&EmuConfig.Cpu.FPUDivFPCR.bitmask)); + armAsm->Msr(a64::FPCR, armLoad64(PTR_CPU(Cpu.FPUDivFPCR.bitmask))); } int sreg, treg; @@ -852,7 +852,7 @@ void recDIV_S_xmm(int info) if (EmuConfig.Cpu.FPUFPCR.bitmask != EmuConfig.Cpu.FPUDivFPCR.bitmask) { // xLDMXCSR(ptr32[&EmuConfig.Cpu.FPUFPCR.bitmask]); - armAsm->Msr(a64::FPCR, armLoadPtr64(&EmuConfig.Cpu.FPUFPCR.bitmask)); + armAsm->Msr(a64::FPCR, armLoad64(PTR_CPU(Cpu.FPUFPCR.bitmask))); } _freeXMMreg(sreg); _freeXMMreg(treg); @@ -1160,7 +1160,7 @@ void recSQRT_S_xmm(int info) roundmode_nearest = EmuConfig.Cpu.FPUFPCR; roundmode_nearest.SetRoundMode(FPRoundMode::Nearest); // xLDMXCSR(ptr32[&roundmode_nearest.bitmask]); - armAsm->Msr(a64::FPCR, armLoadPtr64(&roundmode_nearest.bitmask)); + armAsm->Msr(a64::FPCR, armLoad64(PTR_CPU(Cpu.FPUFPCR.bitmask))); roundmodeFlag = 1; } @@ -1204,7 +1204,7 @@ void recSQRT_S_xmm(int info) if (roundmodeFlag == 1) { // xLDMXCSR(ptr32[&EmuConfig.Cpu.FPUFPCR.bitmask]); - armAsm->Msr(a64::FPCR, armLoadPtr64(&EmuConfig.Cpu.FPUFPCR.bitmask)); + armAsm->Msr(a64::FPCR, armLoad64(PTR_CPU(Cpu.FPUFPCR.bitmask))); } _freeXMMreg(t1reg); @@ -1338,7 +1338,7 @@ void recRSQRT_S_xmm(int info) roundmode_nearest = EmuConfig.Cpu.FPUFPCR; roundmode_nearest.SetRoundMode(FPRoundMode::Nearest); // xLDMXCSR(ptr32[&roundmode_nearest.bitmask]); - armAsm->Msr(a64::FPCR, armLoadPtr64(&roundmode_nearest.bitmask)); + armAsm->Msr(a64::FPCR, armLoad64(PTR_CPU(Cpu.FPUFPCR.bitmask))); roundmodeFlag = true; } @@ -1356,7 +1356,7 @@ void recRSQRT_S_xmm(int info) if (roundmodeFlag) { // xLDMXCSR(ptr32[&EmuConfig.Cpu.FPUFPCR.bitmask]); - armAsm->Msr(a64::FPCR, armLoadPtr64(&EmuConfig.Cpu.FPUFPCR.bitmask)); + armAsm->Msr(a64::FPCR, armLoad64(PTR_CPU(Cpu.FPUFPCR.bitmask))); } } diff --git a/app/src/main/cpp/pcsx2/x86/iR3000A.cpp b/app/src/main/cpp/pcsx2/x86/iR3000A.cpp index cf5ad62..25130d7 100644 --- a/app/src/main/cpp/pcsx2/x86/iR3000A.cpp +++ b/app/src/main/cpp/pcsx2/x86/iR3000A.cpp @@ -47,7 +47,7 @@ extern void psxBREAK(); u32 g_psxMaxRecMem = 0; -uptr psxRecLUT[0x10000]; +alignas(16) uptr psxRecLUT[0x10000]; u32 psxhwLUT[0x10000]; static __fi u32 HWADDR(u32 mem) { return psxhwLUT[mem >> 16] + mem; } @@ -183,9 +183,10 @@ static const void* _DynGen_JITCompile() // xJMP(ptrNative[rbx * (wordsize / 4) + rcx]); armLoad(EAX, PTR_CPU(psxRegs.pc)); - armMoveAddressToReg(RDX, &psxRecLUT); armAsm->Lsr(ECX, EAX, 16); armAsm->Lsr(EAX, EAX, 2); +// armMoveAddressToReg(RDX, &psxRecLUT); + armAsm->Mov(RDX, (uptr)&psxRecLUT); armAsm->Ldr(RCX, a64::MemOperand(RDX, RCX, a64::LSL, 3)); //// armAsm->Ldr(RAX, a64::MemOperand(RCX, RAX, a64::LSL, 3)); @@ -207,9 +208,10 @@ static const void* _DynGen_DispatcherReg() // xJMP(ptrNative[rbx * (wordsize / 4) + rcx]); armLoad(EAX, PTR_CPU(psxRegs.pc)); - armMoveAddressToReg(RDX, &psxRecLUT); armAsm->Lsr(ECX, EAX, 16); armAsm->Lsr(EAX, EAX, 2); +// armMoveAddressToReg(RDX, &psxRecLUT); + armAsm->Mov(RDX, (uptr)&psxRecLUT); armAsm->Ldr(RCX, a64::MemOperand(RDX, RCX, a64::LSL, 3)); //// armAsm->Ldr(RAX, a64::MemOperand(RCX, RAX, a64::LSL, 3)); @@ -237,8 +239,8 @@ static const void* _DynGen_EnterRecompiledCode() // xScopedStackFrame frame(false, true); armBeginStackFrame(); #endif - armMoveAddressToReg(RSTATE_x29, iopMem->Main); +// armAsm->Mov(RSTATE_CPU, (uptr)&g_cpuRegistersPack); // xJMP((void*)iopDispatcherReg); armEmitJmp(iopDispatcherReg); diff --git a/app/src/main/cpp/pcsx2/x86/iR3000A.h b/app/src/main/cpp/pcsx2/x86/iR3000A.h index 627ab95..ea146a3 100644 --- a/app/src/main/cpp/pcsx2/x86/iR3000A.h +++ b/app/src/main/cpp/pcsx2/x86/iR3000A.h @@ -20,7 +20,7 @@ static const int psxInstCycles_Load = 0; #define PSX_HI XMMGPR_HI #define PSX_LO XMMGPR_LO -extern uptr psxRecLUT[]; +alignas(16) extern uptr psxRecLUT[]; void _psxFlushConstReg(int reg); void _psxFlushConstRegs(); diff --git a/app/src/main/cpp/pcsx2/x86/iR3000Atables.cpp b/app/src/main/cpp/pcsx2/x86/iR3000Atables.cpp index e7a1fef..f8b9791 100644 --- a/app/src/main/cpp/pcsx2/x86/iR3000Atables.cpp +++ b/app/src/main/cpp/pcsx2/x86/iR3000Atables.cpp @@ -1171,7 +1171,7 @@ static void rpsxDIVsuper(int info, int sign, int process = 0) // xCMP(ecx, 0); // u8* cont3 = JNE8(0); a64::Label cont3; - armAsm->Cbnz(ECX, &cont3); + armCbnz(ECX, &cont3); //divide by zero // xMOV(edx, eax); diff --git a/app/src/main/cpp/pcsx2/x86/ix86-32/iR5900.cpp b/app/src/main/cpp/pcsx2/x86/ix86-32/iR5900.cpp index eed1dad..f2331ac 100644 --- a/app/src/main/cpp/pcsx2/x86/ix86-32/iR5900.cpp +++ b/app/src/main/cpp/pcsx2/x86/ix86-32/iR5900.cpp @@ -412,9 +412,10 @@ static const void* _DynGen_JITCompile() // xJMP(ptrNative[rbx * (wordsize / 4) + rcx]); armLoad(EAX, PTR_CPU(cpuRegs.pc)); - armMoveAddressToReg(RDX, &recLUT); armAsm->Lsr(ECX, EAX, 16); armAsm->Lsr(EAX, EAX, 2); +// armMoveAddressToReg(RDX, &recLUT); + armAsm->Mov(RDX, (uptr)&recLUT); armAsm->Ldr(RCX, a64::MemOperand(RDX, RCX, a64::LSL, 3)); //// armAsm->Ldr(RAX, a64::MemOperand(RCX, RAX, a64::LSL, 3)); @@ -440,9 +441,10 @@ static const void* _DynGen_DispatcherReg() // xJMP(ptrNative[rbx * (wordsize / 4) + rcx]); armLoad(EAX, PTR_CPU(cpuRegs.pc)); - armMoveAddressToReg(RDX, &recLUT); armAsm->Lsr(ECX, EAX, 16); armAsm->Lsr(EAX, EAX, 2); +// armMoveAddressToReg(RDX, &recLUT); + armAsm->Mov(RDX, (uptr)&recLUT); armAsm->Ldr(RCX, a64::MemOperand(RDX, RCX, a64::LSL, 3)); //// armAsm->Ldr(RAX, a64::MemOperand(RCX, RAX, a64::LSL, 3)); @@ -490,6 +492,7 @@ static const void* _DynGen_EnterRecompiledCode() // From memory to registry armMoveAddressToReg(RSTATE_PSX, &psxRegs); armMoveAddressToReg(RSTATE_CPU, &g_cpuRegistersPack); + armMoveAddressToReg(RSTATE_x26, &eeHw); if (CHECK_FASTMEM) { // xMOV(RFASTMEMBASE, ptrNative[&vtlb_private::vtlbdata.fastmem_base]); diff --git a/app/src/main/cpp/pcsx2/x86/ix86-32/iR5900MultDiv.cpp b/app/src/main/cpp/pcsx2/x86/ix86-32/iR5900MultDiv.cpp index 13e713d..d7c5cd6 100644 --- a/app/src/main/cpp/pcsx2/x86/ix86-32/iR5900MultDiv.cpp +++ b/app/src/main/cpp/pcsx2/x86/ix86-32/iR5900MultDiv.cpp @@ -462,7 +462,7 @@ static void recDIVsuper(int info, bool sign, bool upper, int process) // xCMP(divisor, 0); // u8* cont3 = JNE8(0); a64::Label cont3; - armAsm->Cbnz(divisor, &cont3); + armCbnz(divisor, &cont3); //divide by zero // xMOV(edx, eax); armAsm->Mov(EDX, EAX); diff --git a/app/src/main/cpp/pcsx2/x86/ix86-32/recVTLB.cpp b/app/src/main/cpp/pcsx2/x86/ix86-32/recVTLB.cpp index f2315e1..88650ad 100644 --- a/app/src/main/cpp/pcsx2/x86/ix86-32/recVTLB.cpp +++ b/app/src/main/cpp/pcsx2/x86/ix86-32/recVTLB.cpp @@ -283,7 +283,6 @@ static u8* GetIndirectDispatcherPtr(int mode, int operandsize, int sign = 0) // Generates a JS instruction that targets the appropriate templated instance of // the vtlb Indirect Dispatcher. // - template static void DynGen_HandlerTest(const GenDirectFn& gen_direct, int mode, int bits, bool sign = false) { @@ -326,6 +325,7 @@ static void DynGen_IndirectTlbDispatcher(int mode, int bits, bool sign) #else // xSUB(rsp, 8); // armAsm->Sub(a64::sp, a64::sp, 48); + armAsm->Push(a64::xzr, a64::lr); #endif // xMOVZX(eax, al); @@ -337,20 +337,17 @@ static void DynGen_IndirectTlbDispatcher(int mode, int bits, bool sign) // xSUB(arg1regd, eax); armAsm->Sub(ECX, ECX, EEX); + armAsm->Mov(RAX, RCX); // ecx is address + armAsm->Mov(RCX, RDX); // edx is data + // jump to the indirect handler, which is a C++ function. // [ecx is address, edx is data] // sptr table = (sptr)vtlbdata.RWFT[bits][mode]; // xFastCall(ptrNative[(rax * wordsize) + table], arg1reg, arg2reg); - armAsm->Mov(RXVIXLSCRATCH, reinterpret_cast(vtlbdata.RWFT[bits][mode])); + armAsm->Mov(RXVIXLSCRATCH, (sptr)vtlbdata.RWFT[bits][mode]); armAsm->Ldr(REX, a64::MemOperand(RXVIXLSCRATCH, REX, a64::LSL, 3)); - - armAsm->Mov(RAX, RCX); - armAsm->Mov(RCX, RDX); - - armAsm->Push(a64::xzr, a64::lr); armAsm->Blr(REX); - armAsm->Pop(a64::lr, a64::xzr); if (!mode) { @@ -390,6 +387,7 @@ static void DynGen_IndirectTlbDispatcher(int mode, int bits, bool sign) #else // xADD(rsp, 8); // armAsm->Add(a64::sp, a64::sp, 48); + armAsm->Pop(a64::lr, a64::xzr); #endif // xRET(); @@ -604,23 +602,28 @@ int vtlb_DynGenReadNonQuad_Const(u32 bits, bool sign, bool xmm, u32 addr_const, // Shortcut for the INTC_STAT register, which many games like to spin on heavily. if ((bits == 32) && !EmuConfig.Speedhacks.IntcStat && (paddr == INTC_STAT)) { +// armAsm->Ldr(RXVIXLSCRATCH, (uptr)&psHu32(INTC_STAT)); +// auto mop = a64::MemOperand(RXVIXLSCRATCH); + auto mop = armMemOperandPtr(&psHu32(INTC_STAT)); + // x86_dest_reg = dest_reg_alloc ? dest_reg_alloc() : (_freeX86reg(eax), eax.GetId()); x86_dest_reg = dest_reg_alloc ? dest_reg_alloc() : (_freeX86reg(EAX), EAX.GetCode()); if (!xmm) { + auto regX = a64::XRegister(x86_dest_reg); if (sign) { // xMOVSX(xRegister64(x86_dest_reg), ptr32[&psHu32(INTC_STAT)]); - armAsm->Ldrsw(a64::XRegister(x86_dest_reg), armMemOperandPtr(&psHu32(INTC_STAT))); + armAsm->Ldrsw(regX, mop); } else { // xMOV(xRegister32(x86_dest_reg), ptr32[&psHu32(INTC_STAT)]); - armAsm->Ldr(a64::WRegister(x86_dest_reg), armMemOperandPtr(&psHu32(INTC_STAT))); + armAsm->Ldr(regX.W(), mop); } } else { // xMOVDZX(xRegisterSSE(x86_dest_reg), ptr32[&psHu32(INTC_STAT)]); - armAsm->Ldr(a64::QRegister(x86_dest_reg).S(), armMemOperandPtr(&psHu32(INTC_STAT))); + armAsm->Ldr(a64::QRegister(x86_dest_reg).S(), mop); } } else diff --git a/app/src/main/cpp/pcsx2/x86/microVU_Execute.inl b/app/src/main/cpp/pcsx2/x86/microVU_Execute.inl index 43476ec..24710df 100644 --- a/app/src/main/cpp/pcsx2/x86/microVU_Execute.inl +++ b/app/src/main/cpp/pcsx2/x86/microVU_Execute.inl @@ -44,9 +44,7 @@ void mVUdispatcherAB(mV) // Load VU's MXCSR state if (mvuNeedsFPCRUpdate(mVU)) { // xLDMXCSR(ptr32[isVU0 ? &EmuConfig.Cpu.VU0FPCR.bitmask : &EmuConfig.Cpu.VU1FPCR.bitmask]); - armAsm->Msr(a64::FPCR, isVU0 - ? armLoadPtr64(&EmuConfig.Cpu.VU0FPCR.bitmask) - : armLoadPtr64(&EmuConfig.Cpu.VU1FPCR.bitmask)); + armAsm->Msr(a64::FPCR, armLoad64(isVU0 ? PTR_CPU(Cpu.VU0FPCR.bitmask) : PTR_CPU(Cpu.VU1FPCR.bitmask))); } // Load Regs @@ -107,7 +105,7 @@ void mVUdispatcherAB(mV) // Load EE's MXCSR state if (mvuNeedsFPCRUpdate(mVU)) { // xLDMXCSR(ptr32[&EmuConfig.Cpu.FPUFPCR.bitmask]); - armAsm->Msr(a64::FPCR, armLoadPtr64(&EmuConfig.Cpu.FPUFPCR.bitmask)); + armAsm->Msr(a64::FPCR, armLoad64(PTR_CPU(Cpu.FPUFPCR.bitmask))); } // = The first two DWORD or smaller arguments are passed in ECX and EDX registers; @@ -144,9 +142,7 @@ void mVUdispatcherCD(mV) // Load VU's MXCSR state if (mvuNeedsFPCRUpdate(mVU)) { // xLDMXCSR(ptr32[isVU0 ? &EmuConfig.Cpu.VU0FPCR.bitmask : &EmuConfig.Cpu.VU1FPCR.bitmask]); - armAsm->Msr(a64::FPCR, isVU0 - ? armLoadPtr64(&EmuConfig.Cpu.VU0FPCR.bitmask) - : armLoadPtr64(&EmuConfig.Cpu.VU1FPCR.bitmask)); + armAsm->Msr(a64::FPCR, armLoad64(isVU0 ? PTR_CPU(Cpu.VU0FPCR.bitmask) : PTR_CPU(Cpu.VU1FPCR.bitmask))); } mVUrestoreRegs(mVU); @@ -178,7 +174,7 @@ void mVUdispatcherCD(mV) // Load EE's MXCSR state if (mvuNeedsFPCRUpdate(mVU)) { // xLDMXCSR(ptr32[&EmuConfig.Cpu.FPUFPCR.bitmask]); - armAsm->Msr(a64::FPCR, armLoadPtr64(&EmuConfig.Cpu.FPUFPCR.bitmask)); + armAsm->Msr(a64::FPCR, armLoad64(PTR_CPU(Cpu.FPUFPCR.bitmask))); } armEndStackFrame(); @@ -222,7 +218,7 @@ static void mVUGenerateWaitMTVU(mV) //// // xFastCall((void*)mVUwaitMTVU); armAsm->Push(a64::xzr, a64::lr); - armAsm->Mov(RXVIXLSCRATCH, reinterpret_cast(mVUwaitMTVU)); + armAsm->Ldr(RXVIXLSCRATCH, (uptr)mVUwaitMTVU); armAsm->Blr(RXVIXLSCRATCH); armAsm->Pop(a64::lr, a64::xzr); //// @@ -325,7 +321,7 @@ static void mVUGenerateCompareState(mV) // xForwardJNZ8 exitPoint; a64::Label exitPoint; - armAsm->Cbnz(EAX, &exitPoint); + armCbnz(EAX, &exitPoint); // xMOVAPS (xmm0, ptr32[arg1reg + 0x20]); armAsm->Ldr(xmm0, a64::MemOperand(RCX, 0x20));