From c2644ed27c71de4427bb40795f5e58219281d21f Mon Sep 17 00:00:00 2001 From: k2154 Date: Tue, 29 Jul 2025 23:34:43 +0900 Subject: [PATCH] Android project - cpuRegs, fpuRegs => changed to cpuRegistersPack --- app/src/main/cpp/common/arm64/AsmHelpers.cpp | 4 +- app/src/main/cpp/common/arm64/AsmHelpers.h | 4 +- app/src/main/cpp/pcsx2/x86/iCOP0.cpp | 68 +++--- app/src/main/cpp/pcsx2/x86/iCore.cpp | 55 ++--- app/src/main/cpp/pcsx2/x86/iFPU.cpp | 224 +++++++++--------- app/src/main/cpp/pcsx2/x86/iFPUd.cpp | 56 ++--- app/src/main/cpp/pcsx2/x86/iR5900Misc.cpp | 28 +-- app/src/main/cpp/pcsx2/x86/ix86-32/iCore.cpp | 18 +- app/src/main/cpp/pcsx2/x86/ix86-32/iR5900.cpp | 77 +++--- .../main/cpp/pcsx2/x86/ix86-32/iR5900Arit.cpp | 58 ++--- .../cpp/pcsx2/x86/ix86-32/iR5900AritImm.cpp | 8 +- .../cpp/pcsx2/x86/ix86-32/iR5900Branch.cpp | 24 +- .../main/cpp/pcsx2/x86/ix86-32/iR5900Jump.cpp | 14 +- .../main/cpp/pcsx2/x86/ix86-32/iR5900Move.cpp | 36 +-- .../cpp/pcsx2/x86/ix86-32/iR5900MultDiv.cpp | 68 +++--- .../cpp/pcsx2/x86/ix86-32/iR5900Shift.cpp | 6 +- app/src/main/cpp/pcsx2/x86/microVU_Macro.inl | 14 +- 17 files changed, 380 insertions(+), 382 deletions(-) diff --git a/app/src/main/cpp/common/arm64/AsmHelpers.cpp b/app/src/main/cpp/common/arm64/AsmHelpers.cpp index 298680b..47f3725 100644 --- a/app/src/main/cpp/common/arm64/AsmHelpers.cpp +++ b/app/src/main/cpp/common/arm64/AsmHelpers.cpp @@ -532,8 +532,8 @@ a64::Register armLoadPtr(const void* addr) a64::Register armLoadPtr64(const void* addr) { - armAsm->Ldr(a64::x4, armMemOperandPtr(addr)); - return a64::x4; + armAsm->Ldr(REX, armMemOperandPtr(addr)); + return REX; } a64::Register armLdrh(const void* addr) diff --git a/app/src/main/cpp/common/arm64/AsmHelpers.h b/app/src/main/cpp/common/arm64/AsmHelpers.h index 6bf2b0a..3c55ded 100644 --- a/app/src/main/cpp/common/arm64/AsmHelpers.h +++ b/app/src/main/cpp/common/arm64/AsmHelpers.h @@ -66,12 +66,10 @@ namespace a64 = vixl::aarch64; #define PTR_VUR(field) a64::MemOperand(RSTATE_VUR, offsetof(VURegs, field)) // CPU(iR5900), PSX(iR3000A), FPU(iFPU, iFPUd) -#define RSTATE_FPU a64::x27 #define RSTATE_PSX a64::x28 #define RSTATE_CPU a64::x29 -#define PTR_FPU(field) a64::MemOperand(RSTATE_FPU, offsetof(fpuRegisters, field)) #define PTR_PSX(field) a64::MemOperand(RSTATE_PSX, offsetof(psxRegisters, field)) -#define PTR_CPU(field) a64::MemOperand(RSTATE_CPU, offsetof(cpuRegisters, field)) +#define PTR_CPU(field) a64::MemOperand(RSTATE_CPU, offsetof(cpuRegistersPack, field)) static inline s64 GetPCDisplacement(const void* current, const void* target) diff --git a/app/src/main/cpp/pcsx2/x86/iCOP0.cpp b/app/src/main/cpp/pcsx2/x86/iCOP0.cpp index ee136dd..b1dbdb7 100644 --- a/app/src/main/cpp/pcsx2/x86/iCOP0.cpp +++ b/app/src/main/cpp/pcsx2/x86/iCOP0.cpp @@ -136,7 +136,7 @@ void recDI() recompileNextInstruction(false, false); // DI execution is delayed by one instruction // xMOV(eax, ptr[&cpuRegs.CP0.n.Status]); - armLoad(EAX, PTR_CPU(CP0.n.Status)); + armLoad(EAX, PTR_CPU(cpuRegs.CP0.n.Status)); // xTEST(eax, 0x20006); // EXL | ERL | EDI armAsm->Tst(EAX, 0x20006); // xForwardJNZ8 iHaveNoIdea; @@ -152,7 +152,7 @@ void recDI() // xAND(eax, ~(u32)0x10000); // EIE armAsm->And(EAX, EAX, ~(u32)0x10000); // xMOV(ptr[&cpuRegs.CP0.n.Status], eax); - armStore(PTR_CPU(CP0.n.Status), EAX); + armStore(PTR_CPU(cpuRegs.CP0.n.Status), EAX); // inUserMode.SetTarget(); armBind(&inUserMode); } @@ -173,22 +173,22 @@ void recMFC0() // xMOV(ecx, ptr32[&cpuRegs.cycle]); // xADD(ecx, scaleblockcycles_clear()); // xMOV(ptr32[&cpuRegs.cycle], ecx); // update cycles - armAdd(ECX, PTR_CPU(cycle), scaleblockcycles_clear()); + armAdd(ECX, PTR_CPU(cpuRegs.cycle), scaleblockcycles_clear()); // xMOV(eax, ecx); armAsm->Mov(EAX, ECX); // xSUB(eax, ptr[&cpuRegs.lastCOP0Cycle]); - armAsm->Sub(EAX, EAX, armLoad(PTR_CPU(lastCOP0Cycle))); + armAsm->Sub(EAX, EAX, armLoad(PTR_CPU(cpuRegs.lastCOP0Cycle))); // xADD(ptr[&cpuRegs.CP0.n.Count], eax); - armAdd(PTR_CPU(CP0.n.Count), EAX); + armAdd(PTR_CPU(cpuRegs.CP0.n.Count), EAX); // xMOV(ptr[&cpuRegs.lastCOP0Cycle], ecx); - armStore(PTR_CPU(lastCOP0Cycle), ECX); + armStore(PTR_CPU(cpuRegs.lastCOP0Cycle), ECX); if (!_Rt_) return; const int regt = _Rt_ ? _allocX86reg(X86TYPE_GPR, _Rt_, MODE_WRITE) : -1; // xMOVSX(xRegister64(regt), ptr32[&cpuRegs.CP0.r[_Rd_]]); - armLoadsw(a64::XRegister(regt), PTR_CPU(CP0.r[_Rd_])); + armLoadsw(a64::XRegister(regt), PTR_CPU(cpuRegs.CP0.r[_Rd_])); return; } @@ -201,7 +201,7 @@ void recMFC0() { const int regt = _allocX86reg(X86TYPE_GPR, _Rt_, MODE_WRITE); // xMOVSX(xRegister64(regt), ptr32[&cpuRegs.PERF.n.pccr]); - armLoadsw(a64::XRegister(regt), PTR_CPU(PERF.n.pccr)); + armLoadsw(a64::XRegister(regt), PTR_CPU(cpuRegs.PERF.n.pccr)); } else if (0 == (_Imm_ & 2)) // MFPC 0, only LSB of register matters { @@ -209,13 +209,13 @@ void recMFC0() // xMOV(eax, ptr32[&cpuRegs.cycle]); // xADD(eax, scaleblockcycles_clear()); // xMOV(ptr32[&cpuRegs.cycle], eax); // update cycles - armAdd(PTR_CPU(cycle), scaleblockcycles_clear()); + armAdd(PTR_CPU(cpuRegs.cycle), scaleblockcycles_clear()); // xFastCall((void*)COP0_UpdatePCCR); armEmitCall(reinterpret_cast(COP0_UpdatePCCR)); const int regt = _allocX86reg(X86TYPE_GPR, _Rt_, MODE_WRITE); // xMOVSX(xRegister64(regt), ptr32[&cpuRegs.PERF.n.pcr0]); - armLoadsw(a64::XRegister(regt), PTR_CPU(PERF.n.pcr0)); + armLoadsw(a64::XRegister(regt), PTR_CPU(cpuRegs.PERF.n.pcr0)); } else // MFPC 1 { @@ -223,13 +223,13 @@ void recMFC0() // xMOV(eax, ptr32[&cpuRegs.cycle]); // xADD(eax, scaleblockcycles_clear()); // xMOV(ptr32[&cpuRegs.cycle], eax); // update cycles - armAdd(PTR_CPU(cycle), scaleblockcycles_clear()); + armAdd(PTR_CPU(cpuRegs.cycle), scaleblockcycles_clear()); // xFastCall((void*)COP0_UpdatePCCR); armEmitCall(reinterpret_cast(COP0_UpdatePCCR)); const int regt = _allocX86reg(X86TYPE_GPR, _Rt_, MODE_WRITE); // xMOVSX(xRegister64(regt), ptr32[&cpuRegs.PERF.n.pcr1]); - armLoadsw(a64::XRegister(regt), PTR_CPU(PERF.n.pcr1)); + armLoadsw(a64::XRegister(regt), PTR_CPU(cpuRegs.PERF.n.pcr1)); } return; @@ -242,7 +242,7 @@ void recMFC0() const int regt = _allocX86reg(X86TYPE_GPR, _Rt_, MODE_WRITE); // xMOVSX(xRegister64(regt), ptr32[&cpuRegs.CP0.r[_Rd_]]); - armLoadsw(a64::XRegister(regt), PTR_CPU(CP0.r[_Rd_])); + armLoadsw(a64::XRegister(regt), PTR_CPU(cpuRegs.CP0.r[_Rd_])); } void recMTC0() @@ -256,7 +256,7 @@ void recMTC0() // xMOV(eax, ptr32[&cpuRegs.cycle]); // xADD(eax, scaleblockcycles_clear()); // xMOV(ptr32[&cpuRegs.cycle], eax); // update cycles - armAdd(PTR_CPU(cycle), scaleblockcycles_clear()); + armAdd(PTR_CPU(cpuRegs.cycle), scaleblockcycles_clear()); // xFastCall((void*)WriteCP0Status, g_cpuConstRegs[_Rt_].UL[0]); armAsm->Mov(EAX, g_cpuConstRegs[_Rt_].UL[0]); armEmitCall(reinterpret_cast(WriteCP0Status)); @@ -273,11 +273,11 @@ void recMTC0() // xMOV(ecx, ptr32[&cpuRegs.cycle]); // xADD(ecx, scaleblockcycles_clear()); // xMOV(ptr32[&cpuRegs.cycle], ecx); // update cycles - armAdd(ECX, PTR_CPU(cycle), scaleblockcycles_clear()); + armAdd(ECX, PTR_CPU(cpuRegs.cycle), scaleblockcycles_clear()); // xMOV(ptr[&cpuRegs.lastCOP0Cycle], ecx); - armStore(PTR_CPU(lastCOP0Cycle), ECX); + armStore(PTR_CPU(cpuRegs.lastCOP0Cycle), ECX); // xMOV(ptr32[&cpuRegs.CP0.r[9]], g_cpuConstRegs[_Rt_].UL[0]); - armStore(PTR_CPU(CP0.r[9]), g_cpuConstRegs[_Rt_].UL[0]); + armStore(PTR_CPU(cpuRegs.CP0.r[9]), g_cpuConstRegs[_Rt_].UL[0]); break; case 25: @@ -290,11 +290,11 @@ void recMTC0() // xMOV(eax, ptr32[&cpuRegs.cycle]); // xADD(eax, scaleblockcycles_clear()); // xMOV(ptr32[&cpuRegs.cycle], eax); // update cycles - armAdd(PTR_CPU(cycle), scaleblockcycles_clear()); + armAdd(PTR_CPU(cpuRegs.cycle), scaleblockcycles_clear()); // xFastCall((void*)COP0_UpdatePCCR); armEmitCall(reinterpret_cast(COP0_UpdatePCCR)); // xMOV(ptr32[&cpuRegs.PERF.n.pccr], g_cpuConstRegs[_Rt_].UL[0]); - armStore(PTR_CPU(PERF.n.pccr), g_cpuConstRegs[_Rt_].UL[0]); + armStore(PTR_CPU(cpuRegs.PERF.n.pccr), g_cpuConstRegs[_Rt_].UL[0]); // xFastCall((void*)COP0_DiagnosticPCCR); armEmitCall(reinterpret_cast(COP0_DiagnosticPCCR)); } @@ -303,22 +303,22 @@ void recMTC0() // xMOV(eax, ptr32[&cpuRegs.cycle]); // xADD(eax, scaleblockcycles_clear()); // xMOV(ptr32[&cpuRegs.cycle], eax); // update cycles - armAdd(EAX, PTR_CPU(cycle), scaleblockcycles_clear()); + armAdd(EAX, PTR_CPU(cpuRegs.cycle), scaleblockcycles_clear()); // xMOV(ptr32[&cpuRegs.PERF.n.pcr0], g_cpuConstRegs[_Rt_].UL[0]); - armStore(PTR_CPU(PERF.n.pcr0), g_cpuConstRegs[_Rt_].UL[0]); + armStore(PTR_CPU(cpuRegs.PERF.n.pcr0), g_cpuConstRegs[_Rt_].UL[0]); // xMOV(ptr[&cpuRegs.lastPERFCycle[0]], eax); - armStore(PTR_CPU(lastPERFCycle[0]), EAX); + armStore(PTR_CPU(cpuRegs.lastPERFCycle[0]), EAX); } else // MTPC 1 { // xMOV(eax, ptr32[&cpuRegs.cycle]); // xADD(eax, scaleblockcycles_clear()); // xMOV(ptr32[&cpuRegs.cycle], eax); // update cycles - armAdd(EAX, PTR_CPU(cycle), scaleblockcycles_clear()); + armAdd(EAX, PTR_CPU(cpuRegs.cycle), scaleblockcycles_clear()); // xMOV(ptr32[&cpuRegs.PERF.n.pcr1], g_cpuConstRegs[_Rt_].UL[0]); - armStore(PTR_CPU(PERF.n.pcr1), g_cpuConstRegs[_Rt_].UL[0]); + armStore(PTR_CPU(cpuRegs.PERF.n.pcr1), g_cpuConstRegs[_Rt_].UL[0]); // xMOV(ptr[&cpuRegs.lastPERFCycle[1]], eax); - armStore(PTR_CPU(lastPERFCycle[1]), EAX); + armStore(PTR_CPU(cpuRegs.lastPERFCycle[1]), EAX); } break; @@ -328,7 +328,7 @@ void recMTC0() default: // xMOV(ptr32[&cpuRegs.CP0.r[_Rd_]], g_cpuConstRegs[_Rt_].UL[0]); - armStore(PTR_CPU(CP0.r[_Rd_]), g_cpuConstRegs[_Rt_].UL[0]); + armStore(PTR_CPU(cpuRegs.CP0.r[_Rd_]), g_cpuConstRegs[_Rt_].UL[0]); break; } } @@ -342,7 +342,7 @@ void recMTC0() // xMOV(eax, ptr32[&cpuRegs.cycle]); // xADD(eax, scaleblockcycles_clear()); // xMOV(ptr32[&cpuRegs.cycle], eax); // update cycles - armAdd(PTR_CPU(cycle), scaleblockcycles_clear()); + armAdd(PTR_CPU(cpuRegs.cycle), scaleblockcycles_clear()); // xFastCall((void*)WriteCP0Status); armEmitCall(reinterpret_cast(WriteCP0Status)); break; @@ -358,10 +358,10 @@ void recMTC0() // xMOV(ecx, ptr32[&cpuRegs.cycle]); // xADD(ecx, scaleblockcycles_clear()); // xMOV(ptr32[&cpuRegs.cycle], ecx); // update cycles - armAdd(ECX, PTR_CPU(cycle), scaleblockcycles_clear()); + armAdd(ECX, PTR_CPU(cpuRegs.cycle), scaleblockcycles_clear()); _eeMoveGPRtoM((uptr)&cpuRegs.CP0.r[9], _Rt_); // xMOV(ptr[&cpuRegs.lastCOP0Cycle], ecx); - armStore(PTR_CPU(lastCOP0Cycle), ECX); + armStore(PTR_CPU(cpuRegs.lastCOP0Cycle), ECX); break; case 25: @@ -373,7 +373,7 @@ void recMTC0() // xMOV(eax, ptr32[&cpuRegs.cycle]); // xADD(eax, scaleblockcycles_clear()); // xMOV(ptr32[&cpuRegs.cycle], eax); // update cycles - armAdd(PTR_CPU(cycle), scaleblockcycles_clear()); + armAdd(PTR_CPU(cpuRegs.cycle), scaleblockcycles_clear()); // xFastCall((void*)COP0_UpdatePCCR); armEmitCall(reinterpret_cast(COP0_UpdatePCCR)); _eeMoveGPRtoM((uptr)&cpuRegs.PERF.n.pccr, _Rt_); @@ -385,20 +385,20 @@ void recMTC0() // xMOV(ecx, ptr32[&cpuRegs.cycle]); // xADD(ecx, scaleblockcycles_clear()); // xMOV(ptr32[&cpuRegs.cycle], ecx); // update cycles - armAdd(ECX, PTR_CPU(cycle), scaleblockcycles_clear()); + armAdd(ECX, PTR_CPU(cpuRegs.cycle), scaleblockcycles_clear()); _eeMoveGPRtoM((uptr)&cpuRegs.PERF.n.pcr0, _Rt_); // xMOV(ptr[&cpuRegs.lastPERFCycle[0]], ecx); - armStore(PTR_CPU(lastPERFCycle[0]), ECX); + armStore(PTR_CPU(cpuRegs.lastPERFCycle[0]), ECX); } else // MTPC 1 { // xMOV(ecx, ptr32[&cpuRegs.cycle]); // xADD(ecx, scaleblockcycles_clear()); // xMOV(ptr32[&cpuRegs.cycle], ecx); // update cycles - armAdd(ECX, PTR_CPU(cycle), scaleblockcycles_clear()); + armAdd(ECX, PTR_CPU(cpuRegs.cycle), scaleblockcycles_clear()); _eeMoveGPRtoM((uptr)&cpuRegs.PERF.n.pcr1, _Rt_); // xMOV(ptr[&cpuRegs.lastPERFCycle[1]], ecx); - armStore(PTR_CPU(lastPERFCycle[1]), ECX); + armStore(PTR_CPU(cpuRegs.lastPERFCycle[1]), ECX); } break; diff --git a/app/src/main/cpp/pcsx2/x86/iCore.cpp b/app/src/main/cpp/pcsx2/x86/iCore.cpp index 67bb867..968c10b 100644 --- a/app/src/main/cpp/pcsx2/x86/iCore.cpp +++ b/app/src/main/cpp/pcsx2/x86/iCore.cpp @@ -253,7 +253,7 @@ int _allocFPtoXMMreg(int fpreg, int mode) if (!(xmmregs[i].mode & MODE_READ) && (mode & MODE_READ)) { // xMOVSSZX(xRegisterSSE(i), ptr[&fpuRegs.fpr[fpreg].f]); - armLoad(a64::QRegister(i).S(), PTR_FPU(fpr[fpreg].f)); + armLoad(a64::QRegister(i).S(), PTR_CPU(fpuRegs.fpr[fpreg].f)); xmmregs[i].mode |= MODE_READ; } @@ -276,7 +276,7 @@ int _allocFPtoXMMreg(int fpreg, int mode) if (mode & MODE_READ) { // xMOVSSZX(xRegisterSSE(xmmreg), ptr[&fpuRegs.fpr[fpreg].f]); - armLoad(a64::QRegister(xmmreg).S(), PTR_FPU(fpr[fpreg].f)); + armLoad(a64::QRegister(xmmreg).S(), PTR_CPU(fpuRegs.fpr[fpreg].f)); } return xmmreg; @@ -351,7 +351,7 @@ int _allocGPRtoXMMreg(int gprreg, int mode) // load lower+upper, replace lower // xMOVDQA(xRegisterSSE(xmmreg), ptr128[&cpuRegs.GPR.r[gprreg].UQ]); - armLoad(a64::QRegister(xmmreg).Q(), PTR_CPU(GPR.r[gprreg].UQ)); + armLoad(a64::QRegister(xmmreg).Q(), PTR_CPU(cpuRegs.GPR.r[gprreg].UQ)); // xMOV64(rax, g_cpuConstRegs[gprreg].SD[0]); armAsm->Mov(RAX, g_cpuConstRegs[gprreg].SD[0]); // xPINSR.Q(xRegisterSSE(xmmreg), rax, 0); @@ -372,7 +372,7 @@ int _allocGPRtoXMMreg(int gprreg, int mode) // load lower+upper, replace lower if dirty // xMOVDQA(xRegisterSSE(xmmreg), ptr128[&cpuRegs.GPR.r[gprreg].UQ]); - armLoad(a64::QRegister(xmmreg).Q(), PTR_CPU(GPR.r[gprreg].UQ)); + armLoad(a64::QRegister(xmmreg).Q(), PTR_CPU(cpuRegs.GPR.r[gprreg].UQ)); // if the gpr was written to (dirty), we need to invalidate it if (x86regs[hostx86reg].mode & MODE_WRITE) @@ -389,7 +389,7 @@ int _allocGPRtoXMMreg(int gprreg, int mode) // not loaded RALOG("Loading guest reg %d to host FPR %d\n", gprreg, xmmreg); // xMOVDQA(xRegisterSSE(xmmreg), ptr128[&cpuRegs.GPR.r[gprreg].UQ]); - armLoad(a64::QRegister(xmmreg).Q(), PTR_CPU(GPR.r[gprreg].UQ)); + armLoad(a64::QRegister(xmmreg).Q(), PTR_CPU(cpuRegs.GPR.r[gprreg].UQ)); } } } @@ -424,7 +424,7 @@ int _allocFPACCtoXMMreg(int mode) if (!(xmmregs[i].mode & MODE_READ) && (mode & MODE_READ)) { // xMOVSSZX(xRegisterSSE(i), ptr[&fpuRegs.ACC.f]); - armLoad(a64::QRegister(i).S(), PTR_FPU(ACC.f)); + armLoad(a64::QRegister(i).S(), PTR_CPU(fpuRegs.ACC.f)); xmmregs[i].mode |= MODE_READ; } @@ -448,7 +448,7 @@ int _allocFPACCtoXMMreg(int mode) if (mode & MODE_READ) { // xMOVSSZX(xRegisterSSE(xmmreg), ptr[&fpuRegs.ACC.f]); - armLoad(a64::QRegister(xmmreg).S(), PTR_FPU(ACC.f)); + armLoad(a64::QRegister(xmmreg).S(), PTR_CPU(fpuRegs.ACC.f)); } return xmmreg; @@ -561,21 +561,22 @@ void _addNeededFPACCtoXMMreg() // Written register will set MODE_READ (aka data is valid, no need to load it) void _clearNeededXMMregs() { - for (auto & xmmreg : xmmregs) - { - if (xmmreg.needed) - { - // setup read to any just written regs - if (xmmreg.inuse && (xmmreg.mode & MODE_WRITE)) - xmmreg.mode |= MODE_READ; - xmmreg.needed = 0; - } + u32 i; + for (i = 0; i < iREGCNT_XMM; ++i) + { + if (xmmregs[i].needed) + { + // setup read to any just written regs + if (xmmregs[i].inuse && (xmmregs[i].mode & MODE_WRITE)) + xmmregs[i].mode |= MODE_READ; + xmmregs[i].needed = 0; + } - if (xmmreg.inuse) - { - pxAssert(xmmregs[i].type != XMMTYPE_TEMP); - } - } + if (xmmregs[i].inuse) + { + pxAssert(xmmregs[i].type != XMMTYPE_TEMP); + } + } } // Flush is 0: _freeXMMreg. Flush in memory if MODE_WRITE. Clear inuse @@ -600,7 +601,7 @@ void _deleteGPRtoX86reg(int reg, int flush) { pxAssert(reg != 0); // xMOV(ptr64[&cpuRegs.GPR.r[reg].UL[0]], xRegister64(i)); - armStore(PTR_CPU(GPR.r[reg].UL[0]), a64::XRegister(i)); + armStore(PTR_CPU(cpuRegs.GPR.r[reg].UL[0]), a64::XRegister(i)); // get rid of MODE_WRITE since don't want to flush again x86regs[i].mode &= ~MODE_WRITE; @@ -682,7 +683,7 @@ void _deleteGPRtoXMMreg(int reg, int flush) //pxAssert( g_xmmtypes[i] == XMMT_INT ); // xMOVDQA(ptr[&cpuRegs.GPR.r[reg].UL[0]], xRegisterSSE(i)); - armStore(PTR_CPU(GPR.r[reg].UL[0]), a64::QRegister(i).Q()); + armStore(PTR_CPU(cpuRegs.GPR.r[reg].UL[0]), a64::QRegister(i).Q()); // get rid of MODE_WRITE since don't want to flush again xmmregs[i].mode &= ~MODE_WRITE; @@ -724,7 +725,7 @@ void _deleteFPtoXMMreg(int reg, int flush) if (xmmregs[i].mode & MODE_WRITE) { // xMOVSS(ptr[&fpuRegs.fpr[reg].UL], xRegisterSSE(i)); - armStore(PTR_FPU(fpr[reg].UL), a64::QRegister(i).S()); + armStore(PTR_CPU(fpuRegs.fpr[reg].UL), a64::QRegister(i).S()); // get rid of MODE_WRITE since don't want to flush again xmmregs[i].mode &= ~MODE_WRITE; xmmregs[i].mode |= MODE_READ; @@ -763,17 +764,17 @@ void _writebackXMMreg(int xmmreg) case XMMTYPE_GPRREG: pxAssert(xmmregs[xmmreg].reg != 0); // xMOVDQA(ptr[&cpuRegs.GPR.r[xmmregs[xmmreg].reg].UL[0]], xRegisterSSE(xmmreg)); - armStore(PTR_CPU(GPR.r[xmmregs[xmmreg].reg].UL[0]), a64::QRegister(xmmreg).Q()); + armStore(PTR_CPU(cpuRegs.GPR.r[xmmregs[xmmreg].reg].UL[0]), a64::QRegister(xmmreg).Q()); break; case XMMTYPE_FPREG: // xMOVSS(ptr[&fpuRegs.fpr[xmmregs[xmmreg].reg]], xRegisterSSE(xmmreg)); - armStore(PTR_FPU(fpr[xmmregs[xmmreg].reg]), a64::QRegister(xmmreg).S()); + armStore(PTR_CPU(fpuRegs.fpr[xmmregs[xmmreg].reg]), a64::QRegister(xmmreg).S()); break; case XMMTYPE_FPACC: // xMOVSS(ptr[&fpuRegs.ACC.f], xRegisterSSE(xmmreg)); - armStore(PTR_FPU(ACC.f), a64::QRegister(xmmreg).S()); + armStore(PTR_CPU(fpuRegs.ACC.f), a64::QRegister(xmmreg).S()); break; default: diff --git a/app/src/main/cpp/pcsx2/x86/iFPU.cpp b/app/src/main/cpp/pcsx2/x86/iFPU.cpp index 67f3c6f..93702e4 100644 --- a/app/src/main/cpp/pcsx2/x86/iFPU.cpp +++ b/app/src/main/cpp/pcsx2/x86/iFPU.cpp @@ -117,7 +117,7 @@ void recCFC1(void) auto reg32 = a64::WRegister(regt); // xMOV(xRegister32(regt), ptr32[&fpuRegs.fprc[31]]); - armLoad(reg32, PTR_FPU(fprc[31])); + armLoad(reg32, PTR_CPU(fpuRegs.fprc[31])); // xAND(xRegister32(regt), 0x0083c078); //remove always-zero bits armAsm->And(reg32, reg32, 0x0083c078); // xOR(xRegister32(regt), 0x01000001); //set always-one bits @@ -128,7 +128,7 @@ void recCFC1(void) else { // xMOVSX(xRegister64(regt), ptr32[&fpuRegs.fprc[0]]); - armLoadsw(a64::XRegister(regt), PTR_FPU(fprc[0])); + armLoadsw(a64::XRegister(regt), PTR_CPU(fpuRegs.fprc[0])); } } @@ -141,7 +141,7 @@ void recCTC1() if (GPR_IS_CONST1(_Rt_)) { // xMOV(ptr32[&fpuRegs.fprc[_Fs_]], g_cpuConstRegs[_Rt_].UL[0]); - armStore(PTR_FPU(fprc[_Fs_]), g_cpuConstRegs[_Rt_].UL[0]); + armStore(PTR_CPU(fpuRegs.fprc[_Fs_]), g_cpuConstRegs[_Rt_].UL[0]); } else { @@ -150,21 +150,21 @@ void recCTC1() if (mmreg >= 0) { // xMOVSS(ptr[&fpuRegs.fprc[_Fs_]], xRegisterSSE(mmreg)); - armStore(PTR_FPU(fprc[_Fs_]), a64::QRegister(mmreg).S()); + armStore(PTR_CPU(fpuRegs.fprc[_Fs_]), a64::QRegister(mmreg).S()); } else if ((mmreg = _checkX86reg(X86TYPE_GPR, _Rt_, MODE_READ)) >= 0) { // xMOV(ptr32[&fpuRegs.fprc[_Fs_]], xRegister32(mmreg)); - armStore(PTR_FPU(fprc[_Fs_]), a64::WRegister(mmreg)); + armStore(PTR_CPU(fpuRegs.fprc[_Fs_]), a64::WRegister(mmreg)); } else { _deleteGPRtoXMMreg(_Rt_, 1); // xMOV(eax, ptr[&cpuRegs.GPR.r[_Rt_].UL[0]]); - armLoad(EAX, PTR_CPU(GPR.r[_Rt_].UL[0])); + armLoad(EAX, PTR_CPU(cpuRegs.GPR.r[_Rt_].UL[0])); // xMOV(ptr[&fpuRegs.fprc[_Fs_]], eax); - armStore(PTR_FPU(fprc[_Fs_]), EAX); + armStore(PTR_CPU(fpuRegs.fprc[_Fs_]), EAX); } } } @@ -223,7 +223,7 @@ void recMFC1() { // mem -> gpr // xMOVSX(xRegister64(regt), ptr32[&fpuRegs.fpr[_Fs_].UL]); - armLoadsw(a64::XRegister(regt), PTR_FPU(fpr[_Fs_].UL)); + armLoadsw(a64::XRegister(regt), PTR_CPU(fpuRegs.fpr[_Fs_].UL)); } } @@ -261,7 +261,7 @@ void recMTC1() { pxAssert(!_hasXMMreg(XMMTYPE_FPREG, _Fs_)); // xMOV(ptr32[&fpuRegs.fpr[_Fs_].UL], g_cpuConstRegs[_Rt_].UL[0]); - armStore(PTR_FPU(fpr[_Fs_].UL), g_cpuConstRegs[_Rt_].UL[0]); + armStore(PTR_CPU(fpuRegs.fpr[_Fs_].UL), g_cpuConstRegs[_Rt_].UL[0]); } } else @@ -286,7 +286,7 @@ void recMTC1() } else { // xMOVSS(ptr[&fpuRegs.fpr[_Fs_].UL], xRegisterSSE(xmmgpr)); - armStore(PTR_FPU(fpr[_Fs_].UL), regQ.S()); + armStore(PTR_CPU(fpuRegs.fpr[_Fs_].UL), regQ.S()); } } } @@ -306,7 +306,7 @@ void recMTC1() else { // xMOV(ptr32[&fpuRegs.fpr[_Fs_].UL], xRegister32(regt)); - armStore(PTR_FPU(fpr[_Fs_].UL), reg32); + armStore(PTR_CPU(fpuRegs.fpr[_Fs_].UL), reg32); } } } @@ -430,7 +430,7 @@ void recABS_S_xmm(int info) } else { // xMOVSSZX(xRegisterSSE(EEREC_D), ptr[&fpuRegs.fpr[_Fs_]]); - armLoad(regED.S(), PTR_FPU(fpr[_Fs_])); + armLoad(regED.S(), PTR_CPU(fpuRegs.fpr[_Fs_])); } // xAND.PS(xRegisterSSE(EEREC_D), ptr[&s_pos[0]]); @@ -723,7 +723,7 @@ int recCommutativeOp(int info, int regd, int op) if (regd == EEREC_S) { // xMOVSSZX(xRegisterSSE(t0reg), ptr[&fpuRegs.fpr[_Ft_]]); - armLoad(regT0.S(), PTR_FPU(fpr[_Ft_])); + armLoad(regT0.S(), PTR_CPU(fpuRegs.fpr[_Ft_])); if (CHECK_FPU_EXTRA_OVERFLOW /*&& !CHECK_FPUCLAMPHACK */ || (op >= 2)) { fpuFloat2(regd); @@ -734,7 +734,7 @@ int recCommutativeOp(int info, int regd, int op) else { // xMOVSSZX(xRegisterSSE(regd), ptr[&fpuRegs.fpr[_Ft_]]); - armLoad(regD.S(), PTR_FPU(fpr[_Ft_])); + armLoad(regD.S(), PTR_CPU(fpuRegs.fpr[_Ft_])); if (CHECK_FPU_EXTRA_OVERFLOW || (op >= 2)) { fpuFloat2(regd); @@ -747,7 +747,7 @@ int recCommutativeOp(int info, int regd, int op) if (regd == EEREC_T) { // xMOVSSZX(xRegisterSSE(t0reg), ptr[&fpuRegs.fpr[_Fs_]]); - armLoad(regT0.S(), PTR_FPU(fpr[_Fs_])); + armLoad(regT0.S(), PTR_CPU(fpuRegs.fpr[_Fs_])); if (CHECK_FPU_EXTRA_OVERFLOW || (op >= 2)) { fpuFloat2(regd); @@ -758,7 +758,7 @@ int recCommutativeOp(int info, int regd, int op) else { // xMOVSSZX(xRegisterSSE(regd), ptr[&fpuRegs.fpr[_Fs_]]); - armLoad(regD.S(), PTR_FPU(fpr[_Fs_])); + armLoad(regD.S(), PTR_CPU(fpuRegs.fpr[_Fs_])); if (CHECK_FPU_EXTRA_OVERFLOW || (op >= 2)) { fpuFloat2(regd); @@ -792,9 +792,9 @@ int recCommutativeOp(int info, int regd, int op) default: Console.WriteLn(Color_Magenta, "FPU: recCommutativeOp case 4"); // xMOVSSZX(xRegisterSSE(regd), ptr[&fpuRegs.fpr[_Fs_]]); - armLoad(regD.S(), PTR_FPU(fpr[_Fs_])); + armLoad(regD.S(), PTR_CPU(fpuRegs.fpr[_Fs_])); // xMOVSSZX(xRegisterSSE(t0reg), ptr[&fpuRegs.fpr[_Ft_]]); - armLoad(regT0.S(), PTR_FPU(fpr[_Ft_])); + armLoad(regT0.S(), PTR_CPU(fpuRegs.fpr[_Ft_])); if (CHECK_FPU_EXTRA_OVERFLOW || (op >= 2)) { fpuFloat2(regd); @@ -846,7 +846,7 @@ static void _setupBranchTest() // BC2F checks if the statement is false, BC2T checks if the statement is true. // xMOV(eax, ptr[&fpuRegs.fprc[31]]); - armLoad(EAX, PTR_FPU(fprc[31])); + armLoad(EAX, PTR_CPU(fpuRegs.fprc[31])); // xTEST(eax, FPUflagC); armAsm->Tst(EAX, FPUflagC); } @@ -925,7 +925,7 @@ void recC_EQ_xmm(int info) auto regT0 = a64::QRegister(t0reg); // xMOVSSZX(xRegisterSSE(t0reg), ptr[&fpuRegs.fpr[_Ft_]]); - armLoad(regT0.S(), PTR_FPU(fpr[_Ft_])); + armLoad(regT0.S(), PTR_CPU(fpuRegs.fpr[_Ft_])); fpuFloat3(t0reg); // xUCOMI.SS(xRegisterSSE(regs), xRegisterSSE(t0reg)); @@ -945,7 +945,7 @@ void recC_EQ_xmm(int info) auto regT0 = a64::QRegister(t0reg); // xMOVSSZX(xRegisterSSE(t0reg), ptr[&fpuRegs.fpr[_Fs_]]); - armLoad(regT0.S(), PTR_FPU(fpr[_Fs_])); + armLoad(regT0.S(), PTR_CPU(fpuRegs.fpr[_Fs_])); fpuFloat3(t0reg); // xUCOMI.SS(xRegisterSSE(t0reg), xRegisterSSE(regt)); @@ -975,20 +975,20 @@ void recC_EQ_xmm(int info) default: Console.WriteLn(Color_Magenta, "recC_EQ_xmm: Default"); // xMOV(eax, ptr[&fpuRegs.fpr[_Fs_]]); - armLoad(EAX, PTR_FPU(fpr[_Fs_])); + armLoad(EAX, PTR_CPU(fpuRegs.fpr[_Fs_])); // xCMP(eax, ptr[&fpuRegs.fpr[_Ft_]]); - armAsm->Cmp(EAX, armLoad(PTR_FPU(fpr[_Ft_]))); + armAsm->Cmp(EAX, armLoad(PTR_CPU(fpuRegs.fpr[_Ft_]))); // j8Ptr[0] = JZ8(0); armAsm->B(&j8Ptr0, a64::Condition::eq); // xAND(ptr32[&fpuRegs.fprc[31]], ~FPUflagC); - armAnd(PTR_FPU(fprc[31]), ~FPUflagC); + armAnd(PTR_CPU(fpuRegs.fprc[31]), ~FPUflagC); // j8Ptr[1] = JMP8(0); armAsm->B(&j8Ptr1); // x86SetJ8(j8Ptr[0]); armBind(&j8Ptr0); // xOR(ptr32[&fpuRegs.fprc[31]], FPUflagC); - armOrr(PTR_FPU(fprc[31]), FPUflagC); + armOrr(PTR_CPU(fpuRegs.fprc[31]), FPUflagC); // x86SetJ8(j8Ptr[1]); armBind(&j8Ptr1); return; @@ -997,13 +997,13 @@ void recC_EQ_xmm(int info) // j8Ptr[0] = JZ8(0); armAsm->B(&j8Ptr0, a64::Condition::eq); // xAND(ptr32[&fpuRegs.fprc[31]], ~FPUflagC); - armAnd(PTR_FPU(fprc[31]), ~FPUflagC); + armAnd(PTR_CPU(fpuRegs.fprc[31]), ~FPUflagC); // j8Ptr[1] = JMP8(0); armAsm->B(&j8Ptr1); // x86SetJ8(j8Ptr[0]); armBind(&j8Ptr0); // xOR(ptr32[&fpuRegs.fprc[31]], FPUflagC); - armOrr(PTR_FPU(fprc[31]), FPUflagC); + armOrr(PTR_CPU(fpuRegs.fprc[31]), FPUflagC); // x86SetJ8(j8Ptr[1]); armBind(&j8Ptr1); } @@ -1015,7 +1015,7 @@ void recC_F() { EE::Profiler.EmitOp(eeOpcode::CF_F); // xAND(ptr32[&fpuRegs.fprc[31]], ~FPUflagC); - armAnd(PTR_FPU(fprc[31]), ~FPUflagC); + armAnd(PTR_CPU(fpuRegs.fprc[31]), ~FPUflagC); } //REC_FPUFUNC(C_F); @@ -1038,7 +1038,7 @@ void recC_LE_xmm(int info) auto regT0 = a64::QRegister(t0reg); // xMOVSSZX(xRegisterSSE(t0reg), ptr[&fpuRegs.fpr[_Ft_]]); - armLoad(regT0.S(), PTR_FPU(fpr[_Ft_])); + armLoad(regT0.S(), PTR_CPU(fpuRegs.fpr[_Ft_])); fpuFloat3(t0reg); // xUCOMI.SS(xRegisterSSE(regs), xRegisterSSE(t0reg)); @@ -1058,7 +1058,7 @@ void recC_LE_xmm(int info) auto regT0 = a64::QRegister(t0reg); // xMOVSSZX(xRegisterSSE(t0reg), ptr[&fpuRegs.fpr[_Fs_]]); - armLoad(regT0.S(), PTR_FPU(fpr[_Fs_])); + armLoad(regT0.S(), PTR_CPU(fpuRegs.fpr[_Fs_])); fpuFloat3(t0reg); // xUCOMI.SS(xRegisterSSE(t0reg), xRegisterSSE(regt)); @@ -1088,20 +1088,20 @@ void recC_LE_xmm(int info) default: // Untested and incorrect, but this case is never reached AFAIK (cottonvibes) Console.WriteLn(Color_Magenta, "recC_LE_xmm: Default"); // xMOV(eax, ptr[&fpuRegs.fpr[_Fs_]]); - armLoad(EAX, PTR_FPU(fpr[_Fs_])); + armLoad(EAX, PTR_CPU(fpuRegs.fpr[_Fs_])); // xCMP(eax, ptr[&fpuRegs.fpr[_Ft_]]); - armAsm->Cmp(EAX, armLoad(PTR_FPU(fpr[_Ft_]))); + armAsm->Cmp(EAX, armLoad(PTR_CPU(fpuRegs.fpr[_Ft_]))); // j8Ptr[0] = JLE8(0); armAsm->B(&j8Ptr0, a64::Condition::le); // xAND(ptr32[&fpuRegs.fprc[31]], ~FPUflagC); - armAnd(PTR_FPU(fprc[31]), ~FPUflagC); + armAnd(PTR_CPU(fpuRegs.fprc[31]), ~FPUflagC); // j8Ptr[1] = JMP8(0); armAsm->B(&j8Ptr1); // x86SetJ8(j8Ptr[0]); armBind(&j8Ptr0); // xOR(ptr32[&fpuRegs.fprc[31]], FPUflagC); - armOrr(PTR_FPU(fprc[31]), FPUflagC); + armOrr(PTR_CPU(fpuRegs.fprc[31]), FPUflagC); // x86SetJ8(j8Ptr[1]); armBind(&j8Ptr1); return; @@ -1110,13 +1110,13 @@ void recC_LE_xmm(int info) // j8Ptr[0] = JBE8(0); armAsm->B(&j8Ptr0, a64::Condition::ls); // xAND(ptr32[&fpuRegs.fprc[31]], ~FPUflagC); - armAnd(PTR_FPU(fprc[31]), ~FPUflagC); + armAnd(PTR_CPU(fpuRegs.fprc[31]), ~FPUflagC); // j8Ptr[1] = JMP8(0); armAsm->B(&j8Ptr1); // x86SetJ8(j8Ptr[0]); armBind(&j8Ptr0); // xOR(ptr32[&fpuRegs.fprc[31]], FPUflagC); - armOrr(PTR_FPU(fprc[31]), FPUflagC); + armOrr(PTR_CPU(fpuRegs.fprc[31]), FPUflagC); // x86SetJ8(j8Ptr[1]); armBind(&j8Ptr1); } @@ -1143,7 +1143,7 @@ void recC_LT_xmm(int info) auto regT0 = a64::QRegister(t0reg); // xMOVSSZX(xRegisterSSE(t0reg), ptr[&fpuRegs.fpr[_Ft_]]); - armLoad(regT0.S(), PTR_FPU(fpr[_Ft_])); + armLoad(regT0.S(), PTR_CPU(fpuRegs.fpr[_Ft_])); fpuFloat3(t0reg); // xUCOMI.SS(xRegisterSSE(regs), xRegisterSSE(t0reg)); @@ -1163,7 +1163,7 @@ void recC_LT_xmm(int info) auto regT0 = a64::QRegister(t0reg); // xMOVSSZX(xRegisterSSE(t0reg), ptr[&fpuRegs.fpr[_Fs_]]); - armLoad(regT0.S(), PTR_FPU(fpr[_Fs_])); + armLoad(regT0.S(), PTR_CPU(fpuRegs.fpr[_Fs_])); fpuFloat3(t0reg); // xUCOMI.SS(xRegisterSSE(t0reg), xRegisterSSE(regt)); @@ -1193,20 +1193,20 @@ void recC_LT_xmm(int info) default: Console.WriteLn(Color_Magenta, "recC_LT_xmm: Default"); // xMOV(eax, ptr[&fpuRegs.fpr[_Fs_]]); - armLoad(EAX, PTR_FPU(fpr[_Fs_])); + armLoad(EAX, PTR_CPU(fpuRegs.fpr[_Fs_])); // xCMP(eax, ptr[&fpuRegs.fpr[_Ft_]]); - armAsm->Cmp(EAX, armLoad(PTR_FPU(fpr[_Ft_]))); + armAsm->Cmp(EAX, armLoad(PTR_CPU(fpuRegs.fpr[_Ft_]))); // j8Ptr[0] = JL8(0); armAsm->B(&j8Ptr0, a64::Condition::lt); // xAND(ptr32[&fpuRegs.fprc[31]], ~FPUflagC); - armAnd(PTR_FPU(fprc[31]), ~FPUflagC); + armAnd(PTR_CPU(fpuRegs.fprc[31]), ~FPUflagC); // j8Ptr[1] = JMP8(0); armAsm->B(&j8Ptr1); // x86SetJ8(j8Ptr[0]); armBind(&j8Ptr0); // xOR(ptr32[&fpuRegs.fprc[31]], FPUflagC); - armOrr(PTR_FPU(fprc[31]), FPUflagC); + armOrr(PTR_CPU(fpuRegs.fprc[31]), FPUflagC); // x86SetJ8(j8Ptr[1]); armBind(&j8Ptr1); return; @@ -1215,13 +1215,13 @@ void recC_LT_xmm(int info) // j8Ptr[0] = JB8(0); armAsm->B(&j8Ptr0, a64::Condition::cc); // xAND(ptr32[&fpuRegs.fprc[31]], ~FPUflagC); - armAnd(PTR_FPU(fprc[31]), ~FPUflagC); + armAnd(PTR_CPU(fpuRegs.fprc[31]), ~FPUflagC); // j8Ptr[1] = JMP8(0); armAsm->B(&j8Ptr1); // x86SetJ8(j8Ptr[0]); armBind(&j8Ptr0); // xOR(ptr32[&fpuRegs.fprc[31]], FPUflagC); - armOrr(PTR_FPU(fprc[31]), FPUflagC); + armOrr(PTR_CPU(fpuRegs.fprc[31]), FPUflagC); // x86SetJ8(j8Ptr[1]); armBind(&j8Ptr1); } @@ -1247,7 +1247,7 @@ void recCVT_S_xmm(int info) } else { // xCVTSI2SS(xRegisterSSE(EEREC_D), ptr32[&fpuRegs.fpr[_Fs_]]); - armAsm->Scvtf(regED.S(), armLoad(PTR_FPU(fpr[_Fs_]))); + armAsm->Scvtf(regED.S(), armLoad(PTR_CPU(fpuRegs.fpr[_Fs_]))); } } else @@ -1256,9 +1256,9 @@ void recCVT_S_xmm(int info) auto regTemp = a64::QRegister(temp); // xCVTSI2SS(xRegisterSSE(temp), ptr32[&fpuRegs.fpr[_Fs_]]); - armAsm->Scvtf(regTemp.S(), armLoad(PTR_FPU(fpr[_Fs_]))); + armAsm->Scvtf(regTemp.S(), armLoad(PTR_CPU(fpuRegs.fpr[_Fs_]))); // xMOVSS(ptr32[&fpuRegs.fpr[_Fd_]], xRegisterSSE(temp)); - armStore(PTR_FPU(fpr[_Fd_]), regTemp.S()); + armStore(PTR_CPU(fpuRegs.fpr[_Fd_]), regTemp.S()); _freeXMMreg(temp); } } @@ -1289,9 +1289,9 @@ void recCVT_W() else { // xCVTTSS2SI(eax, ptr32[&fpuRegs.fpr[_Fs_]]); - armAsm->Fcvtzs(EAX, armLoadPtrV(PTR_FPU(fpr[_Fs_])).S()); + armAsm->Fcvtzs(EAX, armLoadPtrV(PTR_CPU(fpuRegs.fpr[_Fs_])).S()); // xMOV(edx, ptr[&fpuRegs.fpr[_Fs_]]); - armLoad(EDX, PTR_FPU(fpr[_Fs_])); + armLoad(EDX, PTR_CPU(fpuRegs.fpr[_Fs_])); } //kill register allocation for dst because we write directly to fpuRegs.fpr[_Fd_] @@ -1308,7 +1308,7 @@ void recCVT_W() //Write the result // xMOV(ptr[&fpuRegs.fpr[_Fd_]], eax); - armStore(PTR_FPU(fpr[_Fd_]), EAX); + armStore(PTR_CPU(fpuRegs.fpr[_Fd_]), EAX); } //------------------------------------------------------------------ @@ -1330,7 +1330,7 @@ void recDIVhelper1(int regd, int regt) // Sets flags auto regT1 = a64::QRegister(t1reg); // xAND(ptr32[&fpuRegs.fprc[31]], ~(FPUflagI | FPUflagD)); // Clear I and D flags - armAnd(PTR_FPU(fprc[31]), ~(FPUflagI | FPUflagD)); + armAnd(PTR_CPU(fpuRegs.fprc[31]), ~(FPUflagI | FPUflagD)); /*--- Check for divide by zero ---*/ // xXOR.PS(xRegisterSSE(t1reg), xRegisterSSE(t1reg)); @@ -1356,13 +1356,13 @@ void recDIVhelper1(int regd, int regt) // Sets flags // pjmp1 = JZ8(0); //Skip if not set armAsm->B(&pjmp1, a64::Condition::eq); // xOR(ptr32[&fpuRegs.fprc[31]], FPUflagI | FPUflagSI); // Set I and SI flags ( 0/0 ) - armOrr(PTR_FPU(fprc[31]), FPUflagI | FPUflagSI); + armOrr(PTR_CPU(fpuRegs.fprc[31]), FPUflagI | FPUflagSI); // pjmp2 = JMP8(0); armAsm->B(&pjmp2); // x86SetJ8(pjmp1); //x/0 but not 0/0 armBind(&pjmp1); // xOR(ptr32[&fpuRegs.fprc[31]], FPUflagD | FPUflagSD); // Set D and SD flags ( x/0 ) - armOrr(PTR_FPU(fprc[31]), FPUflagD | FPUflagSD); + armOrr(PTR_CPU(fpuRegs.fprc[31]), FPUflagD | FPUflagSD); // x86SetJ8(pjmp2); armBind(&pjmp2); @@ -1424,7 +1424,7 @@ void recDIV_S_xmm(int info) // xMOVSS(xRegisterSSE(EEREC_D), xRegisterSSE(EEREC_S)); armAsm->Mov(regED.S(), 0, a64::QRegister(EEREC_S).S(), 0); // xMOVSSZX(xRegisterSSE(t0reg), ptr[&fpuRegs.fpr[_Ft_]]); - armLoad(regT0.S(), PTR_FPU(fpr[_Ft_])); + armLoad(regT0.S(), PTR_CPU(fpuRegs.fpr[_Ft_])); if (CHECK_FPU_EXTRA_FLAGS) recDIVhelper1(EEREC_D, t0reg); else @@ -1437,7 +1437,7 @@ void recDIV_S_xmm(int info) // xMOVSS(xRegisterSSE(t0reg), xRegisterSSE(EEREC_T)); armAsm->Mov(regT0.S(), 0, a64::QRegister(EEREC_T).S(), 0); // xMOVSSZX(xRegisterSSE(EEREC_D), ptr[&fpuRegs.fpr[_Fs_]]); - armLoad(regED.S(), PTR_FPU(fpr[_Fs_])); + armLoad(regED.S(), PTR_CPU(fpuRegs.fpr[_Fs_])); if (CHECK_FPU_EXTRA_FLAGS) recDIVhelper1(EEREC_D, t0reg); else @@ -1446,7 +1446,7 @@ void recDIV_S_xmm(int info) else { // xMOVSSZX(xRegisterSSE(EEREC_D), ptr[&fpuRegs.fpr[_Fs_]]); - armLoad(regED.S(), PTR_FPU(fpr[_Fs_])); + armLoad(regED.S(), PTR_CPU(fpuRegs.fpr[_Fs_])); if (CHECK_FPU_EXTRA_FLAGS) recDIVhelper1(EEREC_D, EEREC_T); else @@ -1479,9 +1479,9 @@ void recDIV_S_xmm(int info) default: //Console.WriteLn("FPU: DIV case 4"); // xMOVSSZX(xRegisterSSE(t0reg), ptr[&fpuRegs.fpr[_Ft_]]); - armLoad(regT0.S(), PTR_FPU(fpr[_Ft_])); + armLoad(regT0.S(), PTR_CPU(fpuRegs.fpr[_Ft_])); // xMOVSSZX(xRegisterSSE(EEREC_D), ptr[&fpuRegs.fpr[_Fs_]]); - armLoad(regED.S(), PTR_FPU(fpr[_Fs_])); + armLoad(regED.S(), PTR_CPU(fpuRegs.fpr[_Fs_])); if (CHECK_FPU_EXTRA_FLAGS) recDIVhelper1(EEREC_D, t0reg); else @@ -1518,7 +1518,7 @@ void recMADDtemp(int info, int regd) if (regd == EEREC_S) { // xMOVSSZX(xRegisterSSE(t0reg), ptr[&fpuRegs.fpr[_Ft_]]); - armLoad(regT0.S(), PTR_FPU(fpr[_Ft_])); + armLoad(regT0.S(), PTR_CPU(fpuRegs.fpr[_Ft_])); if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat2(regd); fpuFloat2(t0reg); } // xMUL.SS(xRegisterSSE(regd), xRegisterSSE(t0reg)); armAsm->Fmul(regD.S(), regD.S(), regT0.S()); @@ -1530,7 +1530,7 @@ void recMADDtemp(int info, int regd) else { // xMOVSSZX(xRegisterSSE(t0reg), ptr[&fpuRegs.ACC]); - armLoad(regT0.S(), PTR_FPU(ACC)); + armLoad(regT0.S(), PTR_CPU(fpuRegs.ACC)); if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(EEREC_ACC); fpuFloat(t0reg); } FPU_ADD(regd, t0reg); } @@ -1538,7 +1538,7 @@ void recMADDtemp(int info, int regd) else if ((info & PROCESS_EE_ACC) && regd == EEREC_ACC) { // xMOVSSZX(xRegisterSSE(t0reg), ptr[&fpuRegs.fpr[_Ft_]]); - armLoad(regT0.S(), PTR_FPU(fpr[_Ft_])); + armLoad(regT0.S(), PTR_CPU(fpuRegs.fpr[_Ft_])); if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat2(EEREC_S); fpuFloat2(t0reg); } // xMUL.SS(xRegisterSSE(t0reg), xRegisterSSE(EEREC_S)); armAsm->Fmul(regT0.S(), regT0.S(), a64::QRegister(EEREC_S).S()); @@ -1548,7 +1548,7 @@ void recMADDtemp(int info, int regd) else { // xMOVSSZX(xRegisterSSE(regd), ptr[&fpuRegs.fpr[_Ft_]]); - armLoad(regD.S(), PTR_FPU(fpr[_Ft_])); + armLoad(regD.S(), PTR_CPU(fpuRegs.fpr[_Ft_])); if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat2(regd); fpuFloat2(EEREC_S); } // xMUL.SS(xRegisterSSE(regd), xRegisterSSE(EEREC_S)); armAsm->Fmul(regD.S(), regD.S(), a64::QRegister(EEREC_S).S()); @@ -1560,7 +1560,7 @@ void recMADDtemp(int info, int regd) else { // xMOVSSZX(xRegisterSSE(t0reg), ptr[&fpuRegs.ACC]); - armLoad(regT0.S(), PTR_FPU(ACC)); + armLoad(regT0.S(), PTR_CPU(fpuRegs.ACC)); if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(EEREC_ACC); fpuFloat(t0reg); } FPU_ADD(regd, t0reg); } @@ -1570,7 +1570,7 @@ void recMADDtemp(int info, int regd) if (regd == EEREC_T) { // xMOVSSZX(xRegisterSSE(t0reg), ptr[&fpuRegs.fpr[_Fs_]]); - armLoad(regT0.S(), PTR_FPU(fpr[_Fs_])); + armLoad(regT0.S(), PTR_CPU(fpuRegs.fpr[_Fs_])); if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat2(regd); fpuFloat2(t0reg); } // xMUL.SS(xRegisterSSE(regd), xRegisterSSE(t0reg)); armAsm->Fmul(regD.S(), regD.S(), regT0.S()); @@ -1582,7 +1582,7 @@ void recMADDtemp(int info, int regd) else { // xMOVSSZX(xRegisterSSE(t0reg), ptr[&fpuRegs.ACC]); - armLoad(regT0.S(), PTR_FPU(ACC)); + armLoad(regT0.S(), PTR_CPU(fpuRegs.ACC)); if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(EEREC_ACC); fpuFloat(t0reg); } FPU_ADD(regd, t0reg); } @@ -1590,7 +1590,7 @@ void recMADDtemp(int info, int regd) else if ((info & PROCESS_EE_ACC) && regd == EEREC_ACC) { // xMOVSSZX(xRegisterSSE(t0reg), ptr[&fpuRegs.fpr[_Fs_]]); - armLoad(regT0.S(), PTR_FPU(fpr[_Fs_])); + armLoad(regT0.S(), PTR_CPU(fpuRegs.fpr[_Fs_])); if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat2(EEREC_T); fpuFloat2(t0reg); } // xMUL.SS(xRegisterSSE(t0reg), xRegisterSSE(EEREC_T)); armAsm->Fmul(regT0.S(), regT0.S(), a64::QRegister(EEREC_T).S()); @@ -1600,7 +1600,7 @@ void recMADDtemp(int info, int regd) else { // xMOVSSZX(xRegisterSSE(regd), ptr[&fpuRegs.fpr[_Fs_]]); - armLoad(regD.S(), PTR_FPU(fpr[_Fs_])); + armLoad(regD.S(), PTR_CPU(fpuRegs.fpr[_Fs_])); if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat2(regd); fpuFloat2(EEREC_T); } // xMUL.SS(xRegisterSSE(regd), xRegisterSSE(EEREC_T)); armAsm->Fmul(regD.S(), regD.S(), a64::QRegister(EEREC_T).S()); @@ -1612,7 +1612,7 @@ void recMADDtemp(int info, int regd) else { // xMOVSSZX(xRegisterSSE(t0reg), ptr[&fpuRegs.ACC]); - armLoad(regT0.S(), PTR_FPU(ACC)); + armLoad(regT0.S(), PTR_CPU(fpuRegs.ACC)); if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(EEREC_ACC); fpuFloat(t0reg); } FPU_ADD(regd, t0reg); } @@ -1632,7 +1632,7 @@ void recMADDtemp(int info, int regd) else { // xMOVSSZX(xRegisterSSE(t0reg), ptr[&fpuRegs.ACC]); - armLoad(regT0.S(), PTR_FPU(ACC)); + armLoad(regT0.S(), PTR_CPU(fpuRegs.ACC)); if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(regd); fpuFloat(t0reg); } FPU_ADD(regd, t0reg); } @@ -1650,7 +1650,7 @@ void recMADDtemp(int info, int regd) else { // xMOVSSZX(xRegisterSSE(t0reg), ptr[&fpuRegs.ACC]); - armLoad(regT0.S(), PTR_FPU(ACC)); + armLoad(regT0.S(), PTR_CPU(fpuRegs.ACC)); if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(regd); fpuFloat(t0reg); } FPU_ADD(regd, t0reg); } @@ -1680,7 +1680,7 @@ void recMADDtemp(int info, int regd) else { // xMOVSSZX(xRegisterSSE(t0reg), ptr[&fpuRegs.ACC]); - armLoad(regT0.S(), PTR_FPU(ACC)); + armLoad(regT0.S(), PTR_CPU(fpuRegs.ACC)); if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(regd); fpuFloat(t0reg); } FPU_ADD(regd, t0reg); } @@ -1691,9 +1691,9 @@ void recMADDtemp(int info, int regd) { const int t1reg = _allocTempXMMreg(XMMT_FPS); // xMOVSSZX(xRegisterSSE(t0reg), ptr[&fpuRegs.fpr[_Fs_]]); - armLoad(regT0.S(), PTR_FPU(fpr[_Fs_])); + armLoad(regT0.S(), PTR_CPU(fpuRegs.fpr[_Fs_])); // xMOVSSZX(xRegisterSSE(t1reg), ptr[&fpuRegs.fpr[_Ft_]]); - armLoad(a64::QRegister(t1reg).S(), PTR_FPU(fpr[_Ft_])); + armLoad(a64::QRegister(t1reg).S(), PTR_CPU(fpuRegs.fpr[_Ft_])); if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat2(t0reg); fpuFloat2(t1reg); } // xMUL.SS(xRegisterSSE(t0reg), xRegisterSSE(t1reg)); armAsm->Fmul(regT0.S(), regT0.S(), a64::QRegister(t1reg).S()); @@ -1704,9 +1704,9 @@ void recMADDtemp(int info, int regd) else { // xMOVSSZX(xRegisterSSE(regd), ptr[&fpuRegs.fpr[_Fs_]]); - armLoad(regD.S(), PTR_FPU(fpr[_Fs_])); + armLoad(regD.S(), PTR_CPU(fpuRegs.fpr[_Fs_])); // xMOVSSZX(xRegisterSSE(t0reg), ptr[&fpuRegs.fpr[_Ft_]]); - armLoad(regT0.S(), PTR_FPU(fpr[_Ft_])); + armLoad(regT0.S(), PTR_CPU(fpuRegs.fpr[_Ft_])); if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat2(regd); fpuFloat2(t0reg); } // xMUL.SS(xRegisterSSE(regd), xRegisterSSE(t0reg)); armAsm->Fmul(regD.S(), regD.S(), regT0.S()); @@ -1718,7 +1718,7 @@ void recMADDtemp(int info, int regd) else { // xMOVSSZX(xRegisterSSE(t0reg), ptr[&fpuRegs.ACC]); - armLoad(regT0.S(), PTR_FPU(ACC)); + armLoad(regT0.S(), PTR_CPU(fpuRegs.ACC)); if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(regd); fpuFloat(t0reg); } FPU_ADD(regd, t0reg); } @@ -1788,7 +1788,7 @@ void recMOV_S_xmm(int info) } else { // xMOVSSZX(xRegisterSSE(EEREC_D), ptr[&fpuRegs.fpr[_Fs_]]); - armLoad(regED.S(), PTR_FPU(fpr[_Fs_])); + armLoad(regED.S(), PTR_CPU(fpuRegs.fpr[_Fs_])); } } @@ -1812,7 +1812,7 @@ void recMSUBtemp(int info, int regd) if (regd == EEREC_S) { // xMOVSSZX(xRegisterSSE(t0reg), ptr[&fpuRegs.fpr[_Ft_]]); - armLoad(regT0.S(), PTR_FPU(fpr[_Ft_])); + armLoad(regT0.S(), PTR_CPU(fpuRegs.fpr[_Ft_])); if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat2(regd); fpuFloat2(t0reg); } // xMUL.SS(xRegisterSSE(regd), xRegisterSSE(t0reg)); armAsm->Fmul(regD.S(), regD.S(), regT0.S()); @@ -1822,7 +1822,7 @@ void recMSUBtemp(int info, int regd) } else { // xMOVSSZX(xRegisterSSE(t0reg), ptr[&fpuRegs.ACC]); - armLoad(regT0.S(), PTR_FPU(ACC)); + armLoad(regT0.S(), PTR_CPU(fpuRegs.ACC)); } if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(regd); fpuFloat(t0reg); } FPU_SUB(t0reg, regd); @@ -1832,7 +1832,7 @@ void recMSUBtemp(int info, int regd) else if ((info & PROCESS_EE_ACC) && regd == EEREC_ACC) { // xMOVSSZX(xRegisterSSE(t0reg), ptr[&fpuRegs.fpr[_Ft_]]); - armLoad(regT0.S(), PTR_FPU(fpr[_Ft_])); + armLoad(regT0.S(), PTR_CPU(fpuRegs.fpr[_Ft_])); if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat2(EEREC_S); fpuFloat2(t0reg); } // xMUL.SS(xRegisterSSE(t0reg), xRegisterSSE(EEREC_S)); armAsm->Fmul(regT0.S(), regT0.S(), a64::QRegister(EEREC_S).S()); @@ -1842,7 +1842,7 @@ void recMSUBtemp(int info, int regd) else { // xMOVSSZX(xRegisterSSE(regd), ptr[&fpuRegs.fpr[_Ft_]]); - armLoad(regD.S(), PTR_FPU(fpr[_Ft_])); + armLoad(regD.S(), PTR_CPU(fpuRegs.fpr[_Ft_])); if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat2(regd); fpuFloat2(EEREC_S); } // xMUL.SS(xRegisterSSE(regd), xRegisterSSE(EEREC_S)); armAsm->Fmul(regD.S(), regD.S(), a64::QRegister(EEREC_S).S()); @@ -1852,7 +1852,7 @@ void recMSUBtemp(int info, int regd) } else { // xMOVSSZX(xRegisterSSE(t0reg), ptr[&fpuRegs.ACC]); - armLoad(regT0.S(), PTR_FPU(ACC)); + armLoad(regT0.S(), PTR_CPU(fpuRegs.ACC)); } if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(regd); fpuFloat(t0reg); } FPU_SUB(t0reg, regd); @@ -1864,7 +1864,7 @@ void recMSUBtemp(int info, int regd) if (regd == EEREC_T) { // xMOVSSZX(xRegisterSSE(t0reg), ptr[&fpuRegs.fpr[_Fs_]]); - armLoad(regT0.S(), PTR_FPU(fpr[_Fs_])); + armLoad(regT0.S(), PTR_CPU(fpuRegs.fpr[_Fs_])); if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat2(regd); fpuFloat2(t0reg); } // xMUL.SS(xRegisterSSE(regd), xRegisterSSE(t0reg)); armAsm->Fmul(regD.S(), regD.S(), regT0.S()); @@ -1874,7 +1874,7 @@ void recMSUBtemp(int info, int regd) } else { // xMOVSSZX(xRegisterSSE(t0reg), ptr[&fpuRegs.ACC]); - armLoad(regT0.S(), PTR_FPU(ACC)); + armLoad(regT0.S(), PTR_CPU(fpuRegs.ACC)); } if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(regd); fpuFloat(t0reg); } FPU_SUB(t0reg, regd); @@ -1884,7 +1884,7 @@ void recMSUBtemp(int info, int regd) else if ((info & PROCESS_EE_ACC) && regd == EEREC_ACC) { // xMOVSSZX(xRegisterSSE(t0reg), ptr[&fpuRegs.fpr[_Fs_]]); - armLoad(regT0.S(), PTR_FPU(fpr[_Fs_])); + armLoad(regT0.S(), PTR_CPU(fpuRegs.fpr[_Fs_])); if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat2(EEREC_T); fpuFloat2(t0reg); } // xMUL.SS(xRegisterSSE(t0reg), xRegisterSSE(EEREC_T)); armAsm->Fmul(regT0.S(), regT0.S(), a64::QRegister(EEREC_T).S()); @@ -1894,7 +1894,7 @@ void recMSUBtemp(int info, int regd) else { // xMOVSSZX(xRegisterSSE(regd), ptr[&fpuRegs.fpr[_Fs_]]); - armLoad(regD.S(), PTR_FPU(fpr[_Fs_])); + armLoad(regD.S(), PTR_CPU(fpuRegs.fpr[_Fs_])); if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat2(regd); fpuFloat2(EEREC_T); } // xMUL.SS(xRegisterSSE(regd), xRegisterSSE(EEREC_T)); armAsm->Fmul(regD.S(), regD.S(), a64::QRegister(EEREC_T).S()); @@ -1904,7 +1904,7 @@ void recMSUBtemp(int info, int regd) } else { // xMOVSSZX(xRegisterSSE(t0reg), ptr[&fpuRegs.ACC]); - armLoad(regT0.S(), PTR_FPU(ACC)); + armLoad(regT0.S(), PTR_CPU(fpuRegs.ACC)); } if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(regd); fpuFloat(t0reg); } FPU_SUB(t0reg, regd); @@ -1924,7 +1924,7 @@ void recMSUBtemp(int info, int regd) } else { // xMOVSSZX(xRegisterSSE(t0reg), ptr[&fpuRegs.ACC]); - armLoad(regT0.S(), PTR_FPU(ACC)); + armLoad(regT0.S(), PTR_CPU(fpuRegs.ACC)); } if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(regd); fpuFloat(t0reg); } FPU_SUB(t0reg, regd); @@ -1942,7 +1942,7 @@ void recMSUBtemp(int info, int regd) } else { // xMOVSSZX(xRegisterSSE(t0reg), ptr[&fpuRegs.ACC]); - armLoad(regT0.S(), PTR_FPU(ACC)); + armLoad(regT0.S(), PTR_CPU(fpuRegs.ACC)); } if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(regd); fpuFloat(t0reg); } FPU_SUB(t0reg, regd); @@ -1972,7 +1972,7 @@ void recMSUBtemp(int info, int regd) } else { // xMOVSSZX(xRegisterSSE(t0reg), ptr[&fpuRegs.ACC]); - armLoad(regT0.S(), PTR_FPU(ACC)); + armLoad(regT0.S(), PTR_CPU(fpuRegs.ACC)); } if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(regd); fpuFloat(t0reg); } FPU_SUB(t0reg, regd); @@ -1985,9 +1985,9 @@ void recMSUBtemp(int info, int regd) { const int t1reg = _allocTempXMMreg(XMMT_FPS); // xMOVSSZX(xRegisterSSE(t0reg), ptr[&fpuRegs.fpr[_Fs_]]); - armLoad(regT0.S(), PTR_FPU(fpr[_Fs_])); + armLoad(regT0.S(), PTR_CPU(fpuRegs.fpr[_Fs_])); // xMOVSSZX(xRegisterSSE(t1reg), ptr[&fpuRegs.fpr[_Ft_]]); - armLoad(a64::QRegister(t1reg).S(), PTR_FPU(fpr[_Ft_])); + armLoad(a64::QRegister(t1reg).S(), PTR_CPU(fpuRegs.fpr[_Ft_])); if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat2(t0reg); fpuFloat2(t1reg); } // xMUL.SS(xRegisterSSE(t0reg), xRegisterSSE(t1reg)); armAsm->Fmul(regT0.S(), regT0.S(), a64::QRegister(t1reg).S()); @@ -1998,9 +1998,9 @@ void recMSUBtemp(int info, int regd) else { // xMOVSSZX(xRegisterSSE(regd), ptr[&fpuRegs.fpr[_Fs_]]); - armLoad(regD.S(), PTR_FPU(fpr[_Fs_])); + armLoad(regD.S(), PTR_CPU(fpuRegs.fpr[_Fs_])); // xMOVSSZX(xRegisterSSE(t0reg), ptr[&fpuRegs.fpr[_Ft_]]); - armLoad(regT0.S(), PTR_FPU(fpr[_Ft_])); + armLoad(regT0.S(), PTR_CPU(fpuRegs.fpr[_Ft_])); if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat2(regd); fpuFloat2(t0reg); } // xMUL.SS(xRegisterSSE(regd), xRegisterSSE(t0reg)); armAsm->Fmul(regD.S(), regD.S(), regT0.S()); @@ -2010,7 +2010,7 @@ void recMSUBtemp(int info, int regd) } else { // xMOVSSZX(xRegisterSSE(t0reg), ptr[&fpuRegs.ACC]); - armLoad(regT0.S(), PTR_FPU(ACC)); + armLoad(regT0.S(), PTR_CPU(fpuRegs.ACC)); } if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(regd); fpuFloat(t0reg); } FPU_SUB(t0reg, regd); @@ -2082,7 +2082,7 @@ void recNEG_S_xmm(int info) } else { // xMOVSSZX(xRegisterSSE(EEREC_D), ptr[&fpuRegs.fpr[_Fs_]]); - armLoad(regED.S(), PTR_FPU(fpr[_Fs_])); + armLoad(regED.S(), PTR_CPU(fpuRegs.fpr[_Fs_])); } //xAND(ptr32[&fpuRegs.fprc[31]], ~(FPUflagO|FPUflagU)); // Clear O and U flags @@ -2125,7 +2125,7 @@ void recSUBop(int info, int regd) armAsm->Mov(regD.S(), 0, a64::QRegister(EEREC_S).S(), 0); } // xMOVSSZX(xRegisterSSE(t0reg), ptr[&fpuRegs.fpr[_Ft_]]); - armLoad(regT0.S(), PTR_FPU(fpr[_Ft_])); + armLoad(regT0.S(), PTR_CPU(fpuRegs.fpr[_Ft_])); recSUBhelper(regd, t0reg); break; case PROCESS_EE_T: @@ -2135,13 +2135,13 @@ void recSUBop(int info, int regd) // xMOVSS(xRegisterSSE(t0reg), xRegisterSSE(EEREC_T)); armAsm->Mov(regT0.S(), 0, a64::QRegister(EEREC_T).S(), 0); // xMOVSSZX(xRegisterSSE(regd), ptr[&fpuRegs.fpr[_Fs_]]); - armLoad(regD.S(), PTR_FPU(fpr[_Fs_])); + armLoad(regD.S(), PTR_CPU(fpuRegs.fpr[_Fs_])); recSUBhelper(regd, t0reg); } else { // xMOVSSZX(xRegisterSSE(regd), ptr[&fpuRegs.fpr[_Fs_]]); - armLoad(regD.S(), PTR_FPU(fpr[_Fs_])); + armLoad(regD.S(), PTR_CPU(fpuRegs.fpr[_Fs_])); recSUBhelper(regd, EEREC_T); } break; @@ -2165,9 +2165,9 @@ void recSUBop(int info, int regd) default: Console.Warning("FPU: SUB case 4"); // xMOVSSZX(xRegisterSSE(t0reg), ptr[&fpuRegs.fpr[_Ft_]]); - armLoad(regT0.S(), PTR_FPU(fpr[_Ft_])); + armLoad(regT0.S(), PTR_CPU(fpuRegs.fpr[_Ft_])); // xMOVSSZX(xRegisterSSE(regd), ptr[&fpuRegs.fpr[_Fs_]]); - armLoad(regD.S(), PTR_FPU(fpr[_Fs_])); + armLoad(regD.S(), PTR_CPU(fpuRegs.fpr[_Fs_])); recSUBhelper(regd, t0reg); break; } @@ -2223,13 +2223,13 @@ void recSQRT_S_xmm(int info) } else { // xMOVSSZX(xRegisterSSE(EEREC_D), ptr[&fpuRegs.fpr[_Ft_]]); - armLoad(regED.S(), PTR_FPU(fpr[_Ft_])); + armLoad(regED.S(), PTR_CPU(fpuRegs.fpr[_Ft_])); } if (CHECK_FPU_EXTRA_FLAGS) { // xAND(ptr32[&fpuRegs.fprc[31]], ~(FPUflagI | FPUflagD)); // Clear I and D flags - armAnd(PTR_FPU(fprc[31]), ~(FPUflagI | FPUflagD)); + armAnd(PTR_CPU(fpuRegs.fprc[31]), ~(FPUflagI | FPUflagD)); /*--- Check for negative SQRT ---*/ // xMOVMSKPS(eax, xRegisterSSE(EEREC_D)); @@ -2240,7 +2240,7 @@ void recSQRT_S_xmm(int info) a64::Label pjmp; armAsm->B(&pjmp, a64::Condition::eq); // xOR(ptr32[&fpuRegs.fprc[31]], FPUflagI | FPUflagSI); // Set I and SI flags - armOrr(PTR_FPU(fprc[31]), FPUflagI | FPUflagSI); + armOrr(PTR_CPU(fpuRegs.fprc[31]), FPUflagI | FPUflagSI); // xAND.PS(xRegisterSSE(EEREC_D), ptr[&s_pos[0]]); // Make EEREC_D Positive armAsm->And(regED.V16B(), regED.V16B(), armLoadPtrV(&s_pos[0]).V16B()); // x86SetJ8(pjmp); @@ -2288,7 +2288,7 @@ void recRSQRThelper1(int regd, int t0reg) // Preforms the RSQRT function when re int t1reg = _allocTempXMMreg(XMMT_FPS); // xAND(ptr32[&fpuRegs.fprc[31]], ~(FPUflagI | FPUflagD)); // Clear I and D flags - armAnd(PTR_FPU(fprc[31]), ~(FPUflagI | FPUflagD)); + armAnd(PTR_CPU(fpuRegs.fprc[31]), ~(FPUflagI | FPUflagD)); /*--- (first) Check for negative SQRT ---*/ // xMOVMSKPS(eax, xRegisterSSE(t0reg)); @@ -2298,7 +2298,7 @@ void recRSQRThelper1(int regd, int t0reg) // Preforms the RSQRT function when re // pjmp2 = JZ8(0); //Skip if not set armAsm->B(&pjmp2, a64::Condition::eq); // xOR(ptr32[&fpuRegs.fprc[31]], FPUflagI | FPUflagSI); // Set I and SI flags - armOrr(PTR_FPU(fprc[31]), FPUflagI | FPUflagSI); + armOrr(PTR_CPU(fpuRegs.fprc[31]), FPUflagI | FPUflagSI); // xAND.PS(xRegisterSSE(t0reg), ptr[&s_pos[0]]); // Make t0reg Positive armAsm->And(regT0.V16B(), regT0.V16B(), armLoadPtrV(&s_pos[0]).V16B()); // Make t0reg Positive // x86SetJ8(pjmp2); @@ -2327,13 +2327,13 @@ void recRSQRThelper1(int regd, int t0reg) // Preforms the RSQRT function when re // qjmp1 = JZ8(0); //Skip if not set armAsm->B(&qjmp1, a64::Condition::eq); // xOR(ptr32[&fpuRegs.fprc[31]], FPUflagI | FPUflagSI); // Set I and SI flags ( 0/0 ) - armOrr(PTR_FPU(fprc[31]), FPUflagI | FPUflagSI); + armOrr(PTR_CPU(fpuRegs.fprc[31]), FPUflagI | FPUflagSI); // qjmp2 = JMP8(0); armAsm->B(&qjmp2); // x86SetJ8(qjmp1); //x/0 but not 0/0 armBind(&qjmp1); // xOR(ptr32[&fpuRegs.fprc[31]], FPUflagD | FPUflagSD); // Set D and SD flags ( x/0 ) - armOrr(PTR_FPU(fprc[31]), FPUflagD | FPUflagSD); + armOrr(PTR_CPU(fpuRegs.fprc[31]), FPUflagD | FPUflagSD); // x86SetJ8(qjmp2); armBind(&qjmp2); @@ -2404,7 +2404,7 @@ void recRSQRT_S_xmm(int info) // xMOVSS(xRegisterSSE(EEREC_D), xRegisterSSE(EEREC_S)); armAsm->Mov(regED.S(), 0, a64::QRegister(EEREC_S).S(), 0); // xMOVSSZX(xRegisterSSE(t0reg), ptr[&fpuRegs.fpr[_Ft_]]); - armLoad(regT0.S(), PTR_FPU(fpr[_Ft_])); + armLoad(regT0.S(), PTR_CPU(fpuRegs.fpr[_Ft_])); if (CHECK_FPU_EXTRA_FLAGS) recRSQRThelper1(EEREC_D, t0reg); else @@ -2415,7 +2415,7 @@ void recRSQRT_S_xmm(int info) // xMOVSS(xRegisterSSE(t0reg), xRegisterSSE(EEREC_T)); armAsm->Mov(regT0.S(), 0, a64::QRegister(EEREC_T).S(), 0); // xMOVSSZX(xRegisterSSE(EEREC_D), ptr[&fpuRegs.fpr[_Fs_]]); - armLoad(regED.S(), PTR_FPU(fpr[_Fs_])); + armLoad(regED.S(), PTR_CPU(fpuRegs.fpr[_Fs_])); if (CHECK_FPU_EXTRA_FLAGS) recRSQRThelper1(EEREC_D, t0reg); else @@ -2435,9 +2435,9 @@ void recRSQRT_S_xmm(int info) default: //Console.WriteLn("FPU: RSQRT case 4"); // xMOVSSZX(xRegisterSSE(t0reg), ptr[&fpuRegs.fpr[_Ft_]]); - armLoad(regT0.S(), PTR_FPU(fpr[_Ft_])); + armLoad(regT0.S(), PTR_CPU(fpuRegs.fpr[_Ft_])); // xMOVSSZX(xRegisterSSE(EEREC_D), ptr[&fpuRegs.fpr[_Fs_]]); - armLoad(regED.S(), PTR_FPU(fpr[_Fs_])); + armLoad(regED.S(), PTR_CPU(fpuRegs.fpr[_Fs_])); if (CHECK_FPU_EXTRA_FLAGS) recRSQRThelper1(EEREC_D, t0reg); else diff --git a/app/src/main/cpp/pcsx2/x86/iFPUd.cpp b/app/src/main/cpp/pcsx2/x86/iFPUd.cpp index 519d6a5..7915130 100644 --- a/app/src/main/cpp/pcsx2/x86/iFPUd.cpp +++ b/app/src/main/cpp/pcsx2/x86/iFPUd.cpp @@ -188,11 +188,11 @@ void ToPS2FPU_Full(int reg, bool flags, int absreg, bool acc, bool addsub) if (flags) { // xAND(ptr32[&fpuRegs.fprc[31]], ~(FPUflagO | FPUflagU)); - armAnd(PTR_FPU(fprc[31]), ~(FPUflagO | FPUflagU)); + armAnd(PTR_CPU(fpuRegs.fprc[31]), ~(FPUflagO | FPUflagU)); } if (flags && acc) { // xAND(ptr32[&fpuRegs.ACCflag], ~1); - armAnd(PTR_FPU(ACCflag), ~1); + armAnd(PTR_CPU(fpuRegs.ACCflag), ~1); } // xMOVAPS(xRegisterSSE(absreg), xRegisterSSE(reg)); @@ -246,11 +246,11 @@ void ToPS2FPU_Full(int reg, bool flags, int absreg, bool acc, bool addsub) armAsm->Orr(regQ.V16B(), regQ.V16B(), armLoadPtrV(&s_const.pos).V16B()); if (flags && FPU_FLAGS_OVERFLOW) { // xOR(ptr32[&fpuRegs.fprc[31]], (FPUflagO | FPUflagSO)); - armOrr(PTR_FPU(fprc[31]), (FPUflagO | FPUflagSO)); + armOrr(PTR_CPU(fpuRegs.fprc[31]), (FPUflagO | FPUflagSO)); } if (flags && FPU_FLAGS_OVERFLOW && acc) { // xOR(ptr32[&fpuRegs.ACCflag], 1); - armOrr(PTR_FPU(ACCflag), 1); + armOrr(PTR_CPU(fpuRegs.ACCflag), 1); } // u8* end3 = JMP8(0); a64::Label end3; @@ -271,7 +271,7 @@ void ToPS2FPU_Full(int reg, bool flags, int absreg, bool acc, bool addsub) armAsm->B(&is_zero, a64::Condition::eq); // xOR(ptr32[&fpuRegs.fprc[31]], (FPUflagU | FPUflagSU)); - armOrr(PTR_FPU(fprc[31]), (FPUflagU | FPUflagSU)); + armOrr(PTR_CPU(fpuRegs.fprc[31]), (FPUflagU | FPUflagSU)); if (addsub) { //On ADD/SUB, the PS2 simply leaves the mantissa bits as they are (after normalization) @@ -355,7 +355,7 @@ void SetMaxValue(int regd) if (info & PROCESS_EE_S) \ armAsm->Mov(a64::QRegister(sreg).S(), 0, a64::QRegister(EEREC_S).S(), 0); \ else \ - armLoad(a64::QRegister(sreg).S(), PTR_FPU(fpr[_Fs_])); \ + armLoad(a64::QRegister(sreg).S(), PTR_CPU(fpuRegs.fpr[_Fs_])); \ } while (0) #define ALLOC_S(sreg) \ @@ -369,7 +369,7 @@ void SetMaxValue(int regd) if (info & PROCESS_EE_T) \ armAsm->Mov(a64::QRegister(treg).S(), 0, a64::QRegister(EEREC_T).S(), 0); \ else \ - armLoad(a64::QRegister(treg).S(), PTR_FPU(fpr[_Ft_])); \ + armLoad(a64::QRegister(treg).S(), PTR_CPU(fpuRegs.fpr[_Ft_])); \ } while (0) #define ALLOC_T(treg) \ @@ -383,7 +383,7 @@ void SetMaxValue(int regd) if (info & PROCESS_EE_ACC) \ armAsm->Mov(a64::QRegister(areg).S(), 0, a64::QRegister(EEREC_ACC).S(), 0); \ else \ - armLoad(a64::QRegister(areg).S(), PTR_FPU(ACC)); \ + armLoad(a64::QRegister(areg).S(), PTR_CPU(fpuRegs.ACC)); \ } while (0) #define ALLOC_ACC(areg) \ @@ -394,7 +394,7 @@ void SetMaxValue(int regd) #define CLEAR_OU_FLAGS \ do { \ - armAnd(PTR_FPU(fprc[31]), ~(FPUflagO | FPUflagU)); \ + armAnd(PTR_CPU(fpuRegs.fprc[31]), ~(FPUflagO | FPUflagU)); \ } while (0) @@ -667,13 +667,13 @@ void recC_EQ_xmm(int info) // j8Ptr[0] = JZ8(0); armAsm->B(&j8Ptr0, a64::Condition::eq); // xAND(ptr32[&fpuRegs.fprc[31]], ~FPUflagC); - armAnd(PTR_FPU(fprc[31]), ~FPUflagC); + armAnd(PTR_CPU(fpuRegs.fprc[31]), ~FPUflagC); // j8Ptr[1] = JMP8(0); armAsm->B(&j8Ptr1); // x86SetJ8(j8Ptr[0]); armBind(&j8Ptr0); // xOR(ptr32[&fpuRegs.fprc[31]], FPUflagC); - armOrr(PTR_FPU(fprc[31]), FPUflagC); + armOrr(PTR_CPU(fpuRegs.fprc[31]), FPUflagC); // x86SetJ8(j8Ptr[1]); armBind(&j8Ptr1); } @@ -690,13 +690,13 @@ void recC_LE_xmm(int info) // j8Ptr[0] = JBE8(0); armAsm->B(&j8Ptr0, a64::Condition::ls); // xAND(ptr32[&fpuRegs.fprc[31]], ~FPUflagC); - armAnd(PTR_FPU(fprc[31]), ~FPUflagC); + armAnd(PTR_CPU(fpuRegs.fprc[31]), ~FPUflagC); // j8Ptr[1] = JMP8(0); armAsm->B(&j8Ptr1); // x86SetJ8(j8Ptr[0]); armBind(&j8Ptr0); // xOR(ptr32[&fpuRegs.fprc[31]], FPUflagC); - armOrr(PTR_FPU(fprc[31]), FPUflagC); + armOrr(PTR_CPU(fpuRegs.fprc[31]), FPUflagC); // x86SetJ8(j8Ptr[1]); armBind(&j8Ptr1); } @@ -713,13 +713,13 @@ void recC_LT_xmm(int info) // j8Ptr[0] = JB8(0); armAsm->B(&j8Ptr0, a64::Condition::cc); // xAND(ptr32[&fpuRegs.fprc[31]], ~FPUflagC); - armAnd(PTR_FPU(fprc[31]), ~FPUflagC); + armAnd(PTR_CPU(fpuRegs.fprc[31]), ~FPUflagC); // j8Ptr[1] = JMP8(0); armAsm->B(&j8Ptr1); // x86SetJ8(j8Ptr[0]); armBind(&j8Ptr0); // xOR(ptr32[&fpuRegs.fprc[31]], FPUflagC); - armOrr(PTR_FPU(fprc[31]), FPUflagC); + armOrr(PTR_CPU(fpuRegs.fprc[31]), FPUflagC); // x86SetJ8(j8Ptr[1]); armBind(&j8Ptr1); } @@ -755,7 +755,7 @@ void recDIVhelper1(int regd, int regt) // Sets flags auto regT1 = a64::QRegister(t1reg); // xAND(ptr32[&fpuRegs.fprc[31]], ~(FPUflagI | FPUflagD)); // Clear I and D flags - armAnd(PTR_FPU(fprc[31]), ~(FPUflagI | FPUflagD)); + armAnd(PTR_CPU(fpuRegs.fprc[31]), ~(FPUflagI | FPUflagD)); //--- Check for divide by zero --- // xXOR.PS(xRegisterSSE(t1reg), xRegisterSSE(t1reg)); @@ -781,13 +781,13 @@ void recDIVhelper1(int regd, int regt) // Sets flags // pjmp1 = JZ8(0); //Skip if not set armAsm->B(&pjmp1, a64::Condition::eq); // xOR(ptr32[&fpuRegs.fprc[31]], FPUflagI | FPUflagSI); // Set I and SI flags ( 0/0 ) - armOrr(PTR_FPU(fprc[31]), FPUflagI | FPUflagSI); + armOrr(PTR_CPU(fpuRegs.fprc[31]), FPUflagI | FPUflagSI); // pjmp2 = JMP8(0); armAsm->B(&pjmp2); // x86SetJ8(pjmp1); //x/0 but not 0/0 armBind(&pjmp1); // xOR(ptr32[&fpuRegs.fprc[31]], FPUflagD | FPUflagSD); // Set D and SD flags ( x/0 ) - armOrr(PTR_FPU(fprc[31]), FPUflagD | FPUflagSD); + armOrr(PTR_CPU(fpuRegs.fprc[31]), FPUflagD | FPUflagSD); // x86SetJ8(pjmp2); armBind(&pjmp2); @@ -892,14 +892,14 @@ void recMaddsub(int info, int regd, int op, bool acc) // xTEST(ptr32[&fpuRegs.fprc[31]], FPUflagO); - armAsm->Tst(armLoad(PTR_FPU(fprc[31])), FPUflagO); + armAsm->Tst(armLoad(PTR_CPU(fpuRegs.fprc[31])), FPUflagO); // u8* mulovf = JNZ8(0); a64::Label mulovf; armAsm->B(&mulovf, a64::Condition::ne); ToDouble(sreg); //else, convert // xTEST(ptr32[&fpuRegs.ACCflag], 1); - armAsm->Tst(armLoad(PTR_FPU(ACCflag)), 1); + armAsm->Tst(armLoad(PTR_CPU(fpuRegs.ACCflag)), 1); // u8* accovf = JNZ8(0); a64::Label accovf; armAsm->B(&accovf, a64::Condition::ne); @@ -923,11 +923,11 @@ void recMaddsub(int info, int regd, int op, bool acc) CLEAR_OU_FLAGS; //clear U flag if (FPU_FLAGS_OVERFLOW) { // xOR(ptr32[&fpuRegs.fprc[31]], FPUflagO | FPUflagSO); - armOrr(PTR_FPU(fprc[31]), FPUflagO | FPUflagSO); + armOrr(PTR_CPU(fpuRegs.fprc[31]), FPUflagO | FPUflagSO); } if (FPU_FLAGS_OVERFLOW && acc) { // xOR(ptr32[&fpuRegs.ACCflag], 1); - armOrr(PTR_FPU(ACCflag), 1); + armOrr(PTR_CPU(fpuRegs.ACCflag), 1); } // u32* skipall = JMP32(0); a64::Label skipall; @@ -1171,7 +1171,7 @@ void recSQRT_S_xmm(int info) if (FPU_FLAGS_ID) { // xAND(ptr32[&fpuRegs.fprc[31]], ~(FPUflagI | FPUflagD)); // Clear I and D flags - armAnd(PTR_FPU(fprc[31]), ~(FPUflagI | FPUflagD)); + armAnd(PTR_CPU(fpuRegs.fprc[31]), ~(FPUflagI | FPUflagD)); //--- Check for negative SQRT --- (sqrt(-0) = 0, unlike what the docs say) // xMOVMSKPS(eax, xRegisterSSE(EEREC_D)); @@ -1182,7 +1182,7 @@ void recSQRT_S_xmm(int info) a64::Label pjmp; armAsm->B(&pjmp, a64::Condition::eq); // xOR(ptr32[&fpuRegs.fprc[31]], FPUflagI | FPUflagSI); // Set I and SI flags - armOrr(PTR_FPU(fprc[31]), FPUflagI | FPUflagSI); + armOrr(PTR_CPU(fpuRegs.fprc[31]), FPUflagI | FPUflagSI); // xAND.PS(xRegisterSSE(EEREC_D), ptr[&s_const.pos[0]]); // Make EEREC_D Positive armAsm->And(regED.V16B(), regED.V16B(), armLoadPtrV(&s_const.pos[0]).V16B()); // x86SetJ8(pjmp); @@ -1233,7 +1233,7 @@ void recRSQRThelper1(int regd, int regt) // Preforms the RSQRT function when reg auto regT1 = a64::QRegister(t1reg); // xAND(ptr32[&fpuRegs.fprc[31]], ~(FPUflagI | FPUflagD)); // Clear I and D flags - armAnd(PTR_FPU(fprc[31]), ~(FPUflagI | FPUflagD)); + armAnd(PTR_CPU(fpuRegs.fprc[31]), ~(FPUflagI | FPUflagD)); //--- (first) Check for negative SQRT --- // xMOVMSKPS(eax, xRegisterSSE(regt)); @@ -1243,7 +1243,7 @@ void recRSQRThelper1(int regd, int regt) // Preforms the RSQRT function when reg // pjmp2 = JZ8(0); //Skip if not set armAsm->B(&pjmp2, a64::Condition::eq); // xOR(ptr32[&fpuRegs.fprc[31]], FPUflagI | FPUflagSI); // Set I and SI flags - armOrr(PTR_FPU(fprc[31]), FPUflagI | FPUflagSI); + armOrr(PTR_CPU(fpuRegs.fprc[31]), FPUflagI | FPUflagSI); // xAND.PS(xRegisterSSE(regt), ptr[&s_const.pos[0]]); // Make regt Positive armAsm->And(regT.V16B(), regT.V16B(), armLoadPtrV(&s_const.pos[0]).V16B()); // x86SetJ8(pjmp2); @@ -1273,13 +1273,13 @@ void recRSQRThelper1(int regd, int regt) // Preforms the RSQRT function when reg // qjmp1 = JZ8(0); //Skip if not set armAsm->B(&qjmp1, a64::Condition::eq); // xOR(ptr32[&fpuRegs.fprc[31]], FPUflagI | FPUflagSI); // Set I and SI flags ( 0/0 ) - armOrr(PTR_FPU(fprc[31]), FPUflagI | FPUflagSI); + armOrr(PTR_CPU(fpuRegs.fprc[31]), FPUflagI | FPUflagSI); // qjmp2 = JMP8(0); armAsm->B(&qjmp2); // x86SetJ8(qjmp1); //x/0 but not 0/0 armBind(&qjmp1); // xOR(ptr32[&fpuRegs.fprc[31]], FPUflagD | FPUflagSD); // Set D and SD flags ( x/0 ) - armOrr(PTR_FPU(fprc[31]), FPUflagD | FPUflagSD); + armOrr(PTR_CPU(fpuRegs.fprc[31]), FPUflagD | FPUflagSD); // x86SetJ8(qjmp2); armBind(&qjmp2); diff --git a/app/src/main/cpp/pcsx2/x86/iR5900Misc.cpp b/app/src/main/cpp/pcsx2/x86/iR5900Misc.cpp index d677e69..293592d 100644 --- a/app/src/main/cpp/pcsx2/x86/iR5900Misc.cpp +++ b/app/src/main/cpp/pcsx2/x86/iR5900Misc.cpp @@ -89,7 +89,7 @@ void recMFSA() // have to zero out bits 63:32 const int temp = _allocTempXMMreg(XMMT_INT); // xMOVSSZX(xRegisterSSE(temp), ptr32[&cpuRegs.sa]); - armLoad(a64::QRegister(temp).S(), PTR_CPU(sa)); + armLoad(a64::QRegister(temp).S(), PTR_CPU(cpuRegs.sa)); // xBLEND.PD(xRegisterSSE(mmreg), xRegisterSSE(temp), 1); armAsm->Mov(a64::QRegister(mmreg).V2D(), 0, a64::QRegister(temp).V2D(), 0); _freeXMMreg(temp); @@ -97,15 +97,15 @@ void recMFSA() else if (const int gprreg = _allocIfUsedGPRtoX86(_Rd_, MODE_WRITE); gprreg >= 0) { // xMOV(xRegister32(gprreg), ptr32[&cpuRegs.sa]); - armLoad(a64::WRegister(gprreg), PTR_CPU(sa)); + armLoad(a64::WRegister(gprreg), PTR_CPU(cpuRegs.sa)); } else { _deleteEEreg(_Rd_, 0); // xMOV(eax, ptr32[&cpuRegs.sa]); - armLoad(EAX, PTR_CPU(sa)); + armLoad(EAX, PTR_CPU(cpuRegs.sa)); // xMOV(ptr64[&cpuRegs.GPR.r[_Rd_].UD[0]], rax); - armStore(PTR_CPU(GPR.r[_Rd_].UD[0]), RAX); + armStore(PTR_CPU(cpuRegs.GPR.r[_Rd_].UD[0]), RAX); } } @@ -115,7 +115,7 @@ void recMTSA() if (GPR_IS_CONST1(_Rs_)) { // xMOV(ptr32[&cpuRegs.sa], g_cpuConstRegs[_Rs_].UL[0] & 0xf); - armStore(PTR_CPU(sa), g_cpuConstRegs[_Rs_].UL[0] & 0xf); + armStore(PTR_CPU(cpuRegs.sa), g_cpuConstRegs[_Rs_].UL[0] & 0xf); } else { @@ -124,22 +124,22 @@ void recMTSA() if ((mmreg = _checkXMMreg(XMMTYPE_GPRREG, _Rs_, MODE_READ)) >= 0) { // xMOVSS(ptr[&cpuRegs.sa], xRegisterSSE(mmreg)); - armStore(PTR_CPU(sa), a64::QRegister(mmreg).S()); + armStore(PTR_CPU(cpuRegs.sa), a64::QRegister(mmreg).S()); } else if ((mmreg = _checkX86reg(X86TYPE_GPR, _Rs_, MODE_READ)) >= 0) { // xMOV(ptr[&cpuRegs.sa], xRegister32(mmreg)); - armStore(PTR_CPU(sa), a64::WRegister(mmreg)); + armStore(PTR_CPU(cpuRegs.sa), a64::WRegister(mmreg)); } else { // xMOV(eax, ptr[&cpuRegs.GPR.r[_Rs_].UL[0]]); - armLoad(EAX, PTR_CPU(GPR.r[_Rs_].UL[0])); + armLoad(EAX, PTR_CPU(cpuRegs.GPR.r[_Rs_].UL[0])); // xMOV(ptr[&cpuRegs.sa], eax); - armStore(PTR_CPU(sa), EAX); + armStore(PTR_CPU(cpuRegs.sa), EAX); } // xAND(ptr32[&cpuRegs.sa], 0xf); - armAnd(PTR_CPU(sa), 0xf); + armAnd(PTR_CPU(cpuRegs.sa), 0xf); } } @@ -148,7 +148,7 @@ void recMTSAB() if (GPR_IS_CONST1(_Rs_)) { // xMOV(ptr32[&cpuRegs.sa], ((g_cpuConstRegs[_Rs_].UL[0] & 0xF) ^ (_Imm_ & 0xF))); - armStore(PTR_CPU(sa), ((g_cpuConstRegs[_Rs_].UL[0] & 0xF) ^ (_Imm_ & 0xF))); + armStore(PTR_CPU(cpuRegs.sa), ((g_cpuConstRegs[_Rs_].UL[0] & 0xF) ^ (_Imm_ & 0xF))); } else { @@ -158,7 +158,7 @@ void recMTSAB() // xXOR(eax, _Imm_ & 0xf); armAsm->Eor(EAX, EAX, _Imm_ & 0xf); // xMOV(ptr[&cpuRegs.sa], eax); - armStore(PTR_CPU(sa), EAX); + armStore(PTR_CPU(cpuRegs.sa), EAX); } } @@ -167,7 +167,7 @@ void recMTSAH() if (GPR_IS_CONST1(_Rs_)) { // xMOV(ptr32[&cpuRegs.sa], ((g_cpuConstRegs[_Rs_].UL[0] & 0x7) ^ (_Imm_ & 0x7)) << 1); - armStore(PTR_CPU(sa), ((g_cpuConstRegs[_Rs_].UL[0] & 0x7) ^ (_Imm_ & 0x7)) << 1); + armStore(PTR_CPU(cpuRegs.sa), ((g_cpuConstRegs[_Rs_].UL[0] & 0x7) ^ (_Imm_ & 0x7)) << 1); } else { @@ -179,7 +179,7 @@ void recMTSAH() // xSHL(eax, 1); armAsm->Lsl(EAX, EAX, 1); // xMOV(ptr[&cpuRegs.sa], eax); - armStore(PTR_CPU(sa), EAX); + armStore(PTR_CPU(cpuRegs.sa), EAX); } } diff --git a/app/src/main/cpp/pcsx2/x86/ix86-32/iCore.cpp b/app/src/main/cpp/pcsx2/x86/ix86-32/iCore.cpp index 851a420..7ec61a3 100644 --- a/app/src/main/cpp/pcsx2/x86/ix86-32/iCore.cpp +++ b/app/src/main/cpp/pcsx2/x86/ix86-32/iCore.cpp @@ -120,7 +120,7 @@ void _flushConstReg(int reg) if (GPR_IS_CONST1(reg) && !(g_cpuFlushedConstReg & (1 << reg))) { // xWriteImm64ToMem(&cpuRegs.GPR.r[reg].UD[0], rax, g_cpuConstRegs[reg].SD[0]); - armStore64(PTR_CPU(GPR.r[reg].UD[0]), g_cpuConstRegs[reg].SD[0]); + armStore64(PTR_CPU(cpuRegs.GPR.r[reg].UD[0]), g_cpuConstRegs[reg].SD[0]); g_cpuFlushedConstReg |= (1 << reg); if (reg == 0) DevCon.Warning("Flushing r0!"); @@ -157,7 +157,7 @@ void _flushConstRegs(bool delete_const) if (g_cpuConstRegs[i].SD[0] == 0) { // xMOV(ptr64[&cpuRegs.GPR.r[i].UD[0]], rax); - armStore(PTR_CPU(GPR.r[i].UD[0]), RAX); + armStore(PTR_CPU(cpuRegs.GPR.r[i].UD[0]), RAX); g_cpuFlushedConstReg |= 1u << i; if (delete_const) g_cpuHasConstReg &= ~(1u << i); @@ -184,7 +184,7 @@ void _flushConstRegs(bool delete_const) if (g_cpuConstRegs[i].SD[0] == -1) { // xMOV(ptr64[&cpuRegs.GPR.r[i].UD[0]], rax); - armStore(PTR_CPU(GPR.r[i].UD[0]), RAX); + armStore(PTR_CPU(cpuRegs.GPR.r[i].UD[0]), RAX); g_cpuFlushedConstReg |= 1u << i; if (delete_const) g_cpuHasConstReg &= ~(1u << i); @@ -199,7 +199,7 @@ void _flushConstRegs(bool delete_const) continue; // xWriteImm64ToMem(&cpuRegs.GPR.r[i].UD[0], rax, g_cpuConstRegs[i].UD[0]); - armStore64(PTR_CPU(GPR.r[i].UD[0]), g_cpuConstRegs[i].UD[0]); + armStore64(PTR_CPU(cpuRegs.GPR.r[i].UD[0]), g_cpuConstRegs[i].UD[0]); g_cpuFlushedConstReg |= 1u << i; if (delete_const) g_cpuHasConstReg &= ~(1u << i); @@ -373,7 +373,7 @@ int _allocX86reg(int type, int reg, int mode) // not loaded RALOG("Loading guest reg %d to GPR %d\n", reg, regnum); // xMOV(new_reg, ptr64[&cpuRegs.GPR.r[reg].UD[0]]); - armLoad(new_reg, PTR_CPU(GPR.r[reg].UD[0])); + armLoad(new_reg, PTR_CPU(cpuRegs.GPR.r[reg].UD[0])); } } } @@ -382,7 +382,7 @@ int _allocX86reg(int type, int reg, int mode) case X86TYPE_FPRC: RALOG("Loading guest reg FPCR %d to GPR %d\n", reg, regnum); // xMOV(xRegister32(regnum), ptr32[&fpuRegs.fprc[reg]]); - armLoad(a64::WRegister(regnum), PTR_FPU(fprc[reg])); + armLoad(a64::WRegister(regnum), PTR_CPU(fpuRegs.fprc[reg])); break; case X86TYPE_PSX: @@ -463,13 +463,13 @@ void _writebackX86Reg(int x86reg) case X86TYPE_GPR: RALOG("Writing back GPR reg %d for guest reg %d P2\n", x86reg, x86regs[x86reg].reg); // xMOV(ptr64[&cpuRegs.GPR.r[x86regs[x86reg].reg].UD[0]], xRegister64(x86reg)); - armStore(PTR_CPU(GPR.r[x86regs[x86reg].reg].UD[0]), a64::XRegister(x86reg)); + armStore(PTR_CPU(cpuRegs.GPR.r[x86regs[x86reg].reg].UD[0]), a64::XRegister(x86reg)); break; case X86TYPE_FPRC: RALOG("Writing back GPR reg %d for guest reg FPCR %d P2\n", x86reg, x86regs[x86reg].reg); // xMOV(ptr32[&fpuRegs.fprc[x86regs[x86reg].reg]], xRegister32(x86reg)); - armStore(PTR_FPU(fprc[x86regs[x86reg].reg]), a64::WRegister(x86reg)); + armStore(PTR_CPU(fpuRegs.fprc[x86regs[x86reg].reg]), a64::WRegister(x86reg)); break; case X86TYPE_VIREG: @@ -481,7 +481,7 @@ void _writebackX86Reg(int x86reg) case X86TYPE_PCWRITEBACK: RALOG("Writing back PC writeback in host reg %d\n", x86reg); // xMOV(ptr32[&cpuRegs.pcWriteback], xRegister32(x86reg)); - armStore(PTR_CPU(pcWriteback), a64::WRegister(x86reg)); + armStore(PTR_CPU(cpuRegs.pcWriteback), a64::WRegister(x86reg)); break; case X86TYPE_PSX: diff --git a/app/src/main/cpp/pcsx2/x86/ix86-32/iR5900.cpp b/app/src/main/cpp/pcsx2/x86/ix86-32/iR5900.cpp index 779aec0..b899807 100644 --- a/app/src/main/cpp/pcsx2/x86/ix86-32/iR5900.cpp +++ b/app/src/main/cpp/pcsx2/x86/ix86-32/iR5900.cpp @@ -267,7 +267,7 @@ void _eeMoveGPRtoR(const a64::WRegister& to, int fromgpr, bool allow_preload) } else { // xMOV(to, ptr[&cpuRegs.GPR.r[fromgpr].UL[0]]); - armLoad(to, PTR_CPU(GPR.r[fromgpr].UL[0])); + armLoad(to, PTR_CPU(cpuRegs.GPR.r[fromgpr].UL[0])); } } } @@ -306,7 +306,7 @@ void _eeMoveGPRtoR(const a64::XRegister& to, int fromgpr, bool allow_preload) } else { // xMOV(to, ptr32[&cpuRegs.GPR.r[fromgpr].UD[0]]); - armLoad(to, PTR_CPU(GPR.r[fromgpr].UD[0])); + armLoad(to, PTR_CPU(cpuRegs.GPR.r[fromgpr].UD[0])); } } } @@ -343,7 +343,7 @@ void _eeMoveGPRtoM(uptr to, int fromgpr) else { // xMOV(eax, ptr32[&cpuRegs.GPR.r[fromgpr].UL[0]]); - armLoad(EAX, PTR_CPU(GPR.r[fromgpr].UL[0])); + armLoad(EAX, PTR_CPU(cpuRegs.GPR.r[fromgpr].UL[0])); // xMOV(ptr32[(void*)(to)], eax); armAsm->Str(EAX, armMemOperandPtr((void*)(to))); } @@ -358,9 +358,9 @@ void recBranchCall(void (*func)()) // to the current cpu cycle. // xMOV(eax, ptr[&cpuRegs.cycle]); - armLoad(EAX, PTR_CPU(cycle)); + armLoad(EAX, PTR_CPU(cpuRegs.cycle)); // xMOV(ptr[&cpuRegs.nextEventCycle], eax); - armStore(PTR_CPU(nextEventCycle), EAX); + armStore(PTR_CPU(cpuRegs.nextEventCycle), EAX); recCall(func); g_branch = 2; @@ -410,7 +410,7 @@ static const void* _DynGen_JITCompile() u8* retval = armGetCurrentCodePointer(); // xFastCall((const void*)recRecompile, ptr32[&cpuRegs.pc]); - armLoad(EAX, PTR_CPU(pc)); + armLoad(EAX, PTR_CPU(cpuRegs.pc)); armEmitCall(reinterpret_cast(recRecompile)); // C equivalent: @@ -423,7 +423,7 @@ static const void* _DynGen_JITCompile() // xMOV(rcx, ptrNative[xComplexAddress(rcx, recLUT, rax * wordsize)]); // xJMP(ptrNative[rbx * (wordsize / 4) + rcx]); - armLoad(EAX, PTR_CPU(pc)); + armLoad(EAX, PTR_CPU(cpuRegs.pc)); armMoveAddressToReg(RDX, &recLUT); armAsm->Lsr(ECX, EAX, 16); armAsm->Lsr(EAX, EAX, 2); @@ -451,7 +451,7 @@ static const void* _DynGen_DispatcherReg() // xMOV(rcx, ptrNative[xComplexAddress(rcx, recLUT, rax * wordsize)]); // xJMP(ptrNative[rbx * (wordsize / 4) + rcx]); - armLoad(EAX, PTR_CPU(pc)); + armLoad(EAX, PTR_CPU(cpuRegs.pc)); armMoveAddressToReg(RDX, &recLUT); armAsm->Lsr(ECX, EAX, 16); armAsm->Lsr(EAX, EAX, 2); @@ -500,9 +500,8 @@ static const void* _DynGen_EnterRecompiledCode() #endif // From memory to registry - armMoveAddressToReg(RSTATE_FPU, &fpuRegs); armMoveAddressToReg(RSTATE_PSX, &psxRegs); - armMoveAddressToReg(RSTATE_CPU, &cpuRegs); + armMoveAddressToReg(RSTATE_CPU, &_cpuRegistersPack); armMoveAddressToReg(RSTATE_VUR, &VU0); if (CHECK_FASTMEM) { @@ -926,15 +925,15 @@ void SetBranchReg(u32 reg) if (x86regs[wbreg].inuse && x86regs[wbreg].type == X86TYPE_PCWRITEBACK) { // xMOV(ptr[&cpuRegs.pc], xRegister32(wbreg)); - armStore(PTR_CPU(pc), a64::WRegister(wbreg)); + armStore(PTR_CPU(cpuRegs.pc), a64::WRegister(wbreg)); x86regs[wbreg].inuse = 0; } else { // xMOV(eax, ptr[&cpuRegs.pcWriteback]); - armLoad(EAX, PTR_CPU(pcWriteback)); + armLoad(EAX, PTR_CPU(cpuRegs.pcWriteback)); // xMOV(ptr[&cpuRegs.pc], eax); - armStore(PTR_CPU(pc), EAX); + armStore(PTR_CPU(cpuRegs.pc), EAX); } } else @@ -943,7 +942,7 @@ void SetBranchReg(u32 reg) { const int x86reg = _allocX86reg(X86TYPE_GPR, reg, MODE_READ); // xMOV(ptr32[&cpuRegs.pc], xRegister32(x86reg)); - armStore(PTR_CPU(pc), a64::WRegister(x86reg)); + armStore(PTR_CPU(cpuRegs.pc), a64::WRegister(x86reg)); } else { @@ -971,7 +970,7 @@ void SetBranchImm(u32 imm) // end the current block iFlushCall(FLUSH_EVERYTHING); // xMOV(ptr32[&cpuRegs.pc], imm); - armStore(PTR_CPU(pc), imm); + armStore(PTR_CPU(cpuRegs.pc), imm); iBranchTest(imm); } @@ -1325,14 +1324,14 @@ void iFlushCall(int flushtype) if ((flushtype & FLUSH_PC) && !g_cpuFlushedPC) { // xMOV(ptr32[&cpuRegs.pc], pc); - armStore(PTR_CPU(pc), pc); + armStore(PTR_CPU(cpuRegs.pc), pc); g_cpuFlushedPC = true; } if ((flushtype & FLUSH_CODE) && !g_cpuFlushedCode) { // xMOV(ptr32[&cpuRegs.code], cpuRegs.code); - armStore(PTR_CPU(code), cpuRegs.code); + armStore(PTR_CPU(cpuRegs.code), cpuRegs.code); g_cpuFlushedCode = true; } @@ -1458,16 +1457,16 @@ static void iBranchTest(u32 newpc) if (EmuConfig.Speedhacks.WaitLoop && s_nBlockFF && newpc == s_branchTo) { // xMOV(eax, ptr32[&cpuRegs.nextEventCycle]); - armLoad(EAX, PTR_CPU(nextEventCycle)); + armLoad(EAX, PTR_CPU(cpuRegs.nextEventCycle)); // xADD(ptr32[&cpuRegs.cycle], scaleblockcycles()); - armAdd(PTR_CPU(cycle), scaleblockcycles()); + armAdd(PTR_CPU(cpuRegs.cycle), scaleblockcycles()); // xCMP(eax, ptr32[&cpuRegs.cycle]); - armLoad(EEX, PTR_CPU(cycle)); + armLoad(EEX, PTR_CPU(cpuRegs.cycle)); armAsm->Cmp(EAX, EEX); // xCMOVS(eax, ptr32[&cpuRegs.cycle]); armAsm->Csel(EAX, EEX, EAX, a64::Condition::mi); // xMOV(ptr32[&cpuRegs.cycle], eax); - armStore(PTR_CPU(cycle), EAX); + armStore(PTR_CPU(cpuRegs.cycle), EAX); // xJMP((void*)DispatcherEvent); armEmitJmp(DispatcherEvent); @@ -1477,9 +1476,9 @@ static void iBranchTest(u32 newpc) // xMOV(eax, ptr[&cpuRegs.cycle]); // xADD(eax, scaleblockcycles()); // xMOV(ptr[&cpuRegs.cycle], eax); // update cycles - armAdd(EAX, PTR_CPU(cycle), scaleblockcycles()); + armAdd(EAX, PTR_CPU(cpuRegs.cycle), scaleblockcycles()); // xSUB(eax, ptr[&cpuRegs.nextEventCycle]); - armAsm->Subs(EAX, EAX, armLoad(PTR_CPU(nextEventCycle))); + armAsm->Subs(EAX, EAX, armLoad(PTR_CPU(cpuRegs.nextEventCycle))); a64::Label labelSigned; armAsm->B(&labelSigned, a64::Condition::pl); @@ -1933,7 +1932,7 @@ void recompileNextInstruction(bool delayslot, bool swapped_delay_slot) g_cpuFlushedCode = false; if (g_maySignalException) { // xAND(ptr32[&cpuRegs.CP0.n.Cause], ~(1 << 31)); // BD - armAnd(PTR_CPU(CP0.n.Cause), ~(1 << 31)); + armAnd(PTR_CPU(cpuRegs.CP0.n.Cause), ~(1 << 31)); } g_recompilingDelaySlot = false; @@ -1967,7 +1966,7 @@ void recompileNextInstruction(bool delayslot, bool swapped_delay_slot) g_cpuFlushedCode = false; if (g_maySignalException) { // xAND(ptr32[&cpuRegs.CP0.n.Cause], ~(1 << 31)); // BD - armAnd(PTR_CPU(CP0.n.Cause), ~(1 << 31)); + armAnd(PTR_CPU(cpuRegs.CP0.n.Cause), ~(1 << 31)); } g_recompilingDelaySlot = false; } @@ -2249,13 +2248,13 @@ static bool skipMPEG_By_Pattern(u32 sPC) if (memRead32(sPC + 8) != p2) return 0; // xMOV(ptr32[&cpuRegs.GPR.n.v0.UL[0]], 1); - armStore(PTR_CPU(GPR.n.v0.UL[0]), 1); + armStore(PTR_CPU(cpuRegs.GPR.n.v0.UL[0]), 1); // xMOV(ptr32[&cpuRegs.GPR.n.v0.UL[1]], 0); - armStore(PTR_CPU(GPR.n.v0.UL[1]), 0); + armStore(PTR_CPU(cpuRegs.GPR.n.v0.UL[1]), 0); // xMOV(eax, ptr32[&cpuRegs.GPR.n.ra.UL[0]]); - armLoad(EAX, PTR_CPU(GPR.n.ra.UL[0])); + armLoad(EAX, PTR_CPU(cpuRegs.GPR.n.ra.UL[0])); // xMOV(ptr32[&cpuRegs.pc], eax); - armStore(PTR_CPU(pc), EAX); + armStore(PTR_CPU(cpuRegs.pc), EAX); iBranchTest(); g_branch = 1; pc = s_nEndBlock; @@ -2283,9 +2282,9 @@ static bool recSkipTimeoutLoop(s32 reg, bool is_timeout_loop) // else new_v0 is 0, so exit loop // xMOV(ebx, ptr32[&cpuRegs.cycle]); // ebx = cycle - armLoad(EBX, PTR_CPU(cycle)); + armLoad(EBX, PTR_CPU(cpuRegs.cycle)); // xMOV(ecx, ptr32[&cpuRegs.nextEventCycle]); // ecx = nextEventCycle - armLoad(ECX, PTR_CPU(nextEventCycle)); + armLoad(ECX, PTR_CPU(cpuRegs.nextEventCycle)); // xCMP(ebx, ecx); armAsm->Cmp(EBX, ECX); //xJAE((void*)DispatcherEvent); // jump to dispatcher if event immediately @@ -2299,14 +2298,14 @@ static bool recSkipTimeoutLoop(s32 reg, bool is_timeout_loop) // xADD(ebx, 8); armAsm->Add(EBX, EBX, 8); // xMOV(ptr32[&cpuRegs.cycle], ebx); - armStore(PTR_CPU(cycle), EBX); + armStore(PTR_CPU(cpuRegs.cycle), EBX); // xJMP((void*)DispatcherEvent); armEmitJmp(DispatcherEvent); // not_dispatcher.SetTarget(); armBind(¬_dispatcher); // xMOV(edx, ptr32[&cpuRegs.GPR.r[reg].UL[0]]); // eax = v0 - armLoad(EDX, PTR_CPU(GPR.r[reg].UL[0])); + armLoad(EDX, PTR_CPU(cpuRegs.GPR.r[reg].UL[0])); // xLEA(rax, ptrNative[rdx * 8 + rbx]); // edx = v0 * 8 + cycle armAsm->Add(RAX, RBX, a64::Operand(RDX, a64::LSL, 3)); // xCMP(rcx, rax); @@ -2314,7 +2313,7 @@ static bool recSkipTimeoutLoop(s32 reg, bool is_timeout_loop) // xCMOVB(rax, rcx); // eax = new_cycles = min(v8 * 8, nextEventCycle) armAsm->Csel(RAX, RCX, RAX, a64::Condition::cc); // xMOV(ptr32[&cpuRegs.cycle], eax); // writeback new_cycles - armStore(PTR_CPU(cycle), EAX); + armStore(PTR_CPU(cpuRegs.cycle), EAX); // xSUB(eax, ebx); // new_cycles -= cycle armAsm->Sub(EAX, EAX, EBX); // xSHR(eax, 3); // compute new v0 value @@ -2322,11 +2321,11 @@ static bool recSkipTimeoutLoop(s32 reg, bool is_timeout_loop) // xSUB(edx, eax); // v0 -= cycle_diff armAsm->Subs(EDX, EDX, EAX); // xMOV(ptr32[&cpuRegs.GPR.r[reg].UL[0]], edx); // write back new value of v0 - armStore(PTR_CPU(GPR.r[reg].UL[0]), EDX); + armStore(PTR_CPU(cpuRegs.GPR.r[reg].UL[0]), EDX); // xJNZ((void*)DispatcherEvent); // jump to dispatcher if new v0 is not zero (i.e. an event) armEmitCondBranch(a64::ne, DispatcherEvent); // xMOV(ptr32[&cpuRegs.pc], s_nEndBlock); // otherwise end of loop - armStore(PTR_CPU(pc), s_nEndBlock); + armStore(PTR_CPU(cpuRegs.pc), s_nEndBlock); // recBlocks.Link(HWADDR(s_nEndBlock), xJcc32()); armAsm->Nop(); recBlocks.Link(HWADDR(s_nEndBlock), (s32*)armGetCurrentCodePointer()-1); @@ -2437,7 +2436,7 @@ static void recRecompile(const u32 startpc) eeRecNeedsReset = true; // 0x3563b8 is the start address of the function that invalidate entry in TLB cache // xFastCall((void*)GoemonUnloadTlb, ptr32[&cpuRegs.GPR.n.a0.UL[0]]); - armLoad(EAX, PTR_CPU(GPR.n.a0.UL[0])); + armLoad(EAX, PTR_CPU(cpuRegs.GPR.n.a0.UL[0])); armEmitCall(reinterpret_cast(GoemonUnloadTlb)); } } @@ -2885,9 +2884,9 @@ StartRecomp: else { // xMOV(ptr32[&cpuRegs.pc], pc); - armStore(PTR_CPU(pc), pc); + armStore(PTR_CPU(cpuRegs.pc), pc); // xADD(ptr32[&cpuRegs.cycle], scaleblockcycles()); - armAdd(PTR_CPU(cycle), scaleblockcycles()); + armAdd(PTR_CPU(cpuRegs.cycle), scaleblockcycles()); // recBlocks.Link(HWADDR(pc), xJcc32()); armAsm->Nop(); recBlocks.Link(HWADDR(pc), (s32*)armGetCurrentCodePointer()-1); diff --git a/app/src/main/cpp/pcsx2/x86/ix86-32/iR5900Arit.cpp b/app/src/main/cpp/pcsx2/x86/ix86-32/iR5900Arit.cpp index f8a47a0..42bd39a 100644 --- a/app/src/main/cpp/pcsx2/x86/ix86-32/iR5900Arit.cpp +++ b/app/src/main/cpp/pcsx2/x86/ix86-32/iR5900Arit.cpp @@ -47,7 +47,7 @@ static void recMoveStoD(int info) } else { // xMOV(xRegister32(EEREC_D), ptr32[&cpuRegs.GPR.r[_Rs_].UL[0]]); - armLoad(a64::WRegister(EEREC_D), PTR_CPU(GPR.r[_Rs_].UL[0])); + armLoad(a64::WRegister(EEREC_D), PTR_CPU(cpuRegs.GPR.r[_Rs_].UL[0])); } } @@ -59,7 +59,7 @@ static void recMoveStoD64(int info) } else { // xMOV(xRegister64(EEREC_D), ptr64[&cpuRegs.GPR.r[_Rs_].UD[0]]); - armLoad(a64::XRegister(EEREC_D), PTR_CPU(GPR.r[_Rs_].UD[0])); + armLoad(a64::XRegister(EEREC_D), PTR_CPU(cpuRegs.GPR.r[_Rs_].UD[0])); } } @@ -71,7 +71,7 @@ static void recMoveTtoD(int info) } else { // xMOV(xRegister32(EEREC_D), ptr32[&cpuRegs.GPR.r[_Rt_].UL[0]]); - armLoad(a64::WRegister(EEREC_D), PTR_CPU(GPR.r[_Rt_].UL[0])); + armLoad(a64::WRegister(EEREC_D), PTR_CPU(cpuRegs.GPR.r[_Rt_].UL[0])); } } @@ -83,7 +83,7 @@ static void recMoveTtoD64(int info) } else { // xMOV(xRegister64(EEREC_D), ptr64[&cpuRegs.GPR.r[_Rt_].UD[0]]); - armLoad(a64::XRegister(EEREC_D), PTR_CPU(GPR.r[_Rt_].UD[0])); + armLoad(a64::XRegister(EEREC_D), PTR_CPU(cpuRegs.GPR.r[_Rt_].UD[0])); } } @@ -155,21 +155,21 @@ static void recADD_(int info) // xMOV(xRegister32(EEREC_D), xRegister32(EEREC_S)); armAsm->Mov(reg32, a64::WRegister(EEREC_S)); // xADD(xRegister32(EEREC_D), ptr32[&cpuRegs.GPR.r[_Rt_].UD[0]]); - armAsm->Add(reg32, reg32, armLoad(PTR_CPU(GPR.r[_Rt_].UD[0]))); + armAsm->Add(reg32, reg32, armLoad(PTR_CPU(cpuRegs.GPR.r[_Rt_].UD[0]))); } else if (info & PROCESS_EE_T) { // xMOV(xRegister32(EEREC_D), xRegister32(EEREC_T)); armAsm->Mov(reg32, a64::WRegister(EEREC_T)); // xADD(xRegister32(EEREC_D), ptr32[&cpuRegs.GPR.r[_Rs_].UD[0]]); - armAsm->Add(reg32, reg32, armLoad(PTR_CPU(GPR.r[_Rs_].UD[0]))); + armAsm->Add(reg32, reg32, armLoad(PTR_CPU(cpuRegs.GPR.r[_Rs_].UD[0]))); } else { // xMOV(xRegister32(EEREC_D), ptr32[&cpuRegs.GPR.r[_Rs_].UD[0]]); - armLoad(reg32, PTR_CPU(GPR.r[_Rs_].UD[0])); + armLoad(reg32, PTR_CPU(cpuRegs.GPR.r[_Rs_].UD[0])); // xADD(xRegister32(EEREC_D), ptr32[&cpuRegs.GPR.r[_Rt_].UD[0]]); - armAsm->Add(reg32, reg32, armLoad(PTR_CPU(GPR.r[_Rt_].UD[0]))); + armAsm->Add(reg32, reg32, armLoad(PTR_CPU(cpuRegs.GPR.r[_Rt_].UD[0]))); } // xMOVSX(xRegister64(EEREC_D), xRegister32(EEREC_D)); @@ -248,21 +248,21 @@ static void recDADD_(int info) // xMOV(xRegister64(EEREC_D), xRegister64(EEREC_S)); armAsm->Mov(reg64, a64::XRegister(EEREC_S)); // xADD(xRegister64(EEREC_D), ptr64[&cpuRegs.GPR.r[_Rt_].UD[0]]); - armAsm->Add(reg64, reg64, armLoad64(PTR_CPU(GPR.r[_Rt_].UD[0]))); + armAsm->Add(reg64, reg64, armLoad64(PTR_CPU(cpuRegs.GPR.r[_Rt_].UD[0]))); } else if (info & PROCESS_EE_T) { // xMOV(xRegister64(EEREC_D), xRegister64(EEREC_T)); armAsm->Mov(reg64, a64::XRegister(EEREC_T)); // xADD(xRegister64(EEREC_D), ptr64[&cpuRegs.GPR.r[_Rs_].UD[0]]); - armAsm->Add(reg64, reg64, armLoad64(PTR_CPU(GPR.r[_Rs_].UD[0]))); + armAsm->Add(reg64, reg64, armLoad64(PTR_CPU(cpuRegs.GPR.r[_Rs_].UD[0]))); } else { // xMOV(xRegister64(EEREC_D), ptr64[&cpuRegs.GPR.r[_Rs_].UD[0]]); - armLoad(reg64, PTR_CPU(GPR.r[_Rs_].UD[0])); + armLoad(reg64, PTR_CPU(cpuRegs.GPR.r[_Rs_].UD[0])); // xADD(xRegister64(EEREC_D), ptr64[&cpuRegs.GPR.r[_Rt_].UD[0]]); - armAsm->Add(reg64, reg64, armLoad64(PTR_CPU(GPR.r[_Rt_].UD[0]))); + armAsm->Add(reg64, reg64, armLoad64(PTR_CPU(cpuRegs.GPR.r[_Rt_].UD[0]))); } } @@ -295,7 +295,7 @@ static void recSUB_consts(int info) } else { // xSUB(eax, ptr32[&cpuRegs.GPR.r[_Rt_].SL[0]]); - armAsm->Sub(EAX, EAX, armLoad(PTR_CPU(GPR.r[_Rt_].SL[0]))); + armAsm->Sub(EAX, EAX, armLoad(PTR_CPU(cpuRegs.GPR.r[_Rt_].SL[0]))); } // xMOVSX(xRegister64(EEREC_D), eax); @@ -365,7 +365,7 @@ static void recSUB_(int info) // xMOV(xRegister32(EEREC_D), xRegister32(EEREC_S)); armAsm->Mov(reg32, a64::WRegister(EEREC_S)); // xSUB(xRegister32(EEREC_D), ptr32[&cpuRegs.GPR.r[_Rt_].UL[0]]); - armAsm->Sub(reg32, reg32, armLoad(PTR_CPU(GPR.r[_Rt_].UL[0]))); + armAsm->Sub(reg32, reg32, armLoad(PTR_CPU(cpuRegs.GPR.r[_Rt_].UL[0]))); // xMOVSX(xRegister64(EEREC_D), xRegister32(EEREC_D)); armAsm->Sxtw(a64::XRegister(EEREC_D), reg32); } @@ -373,7 +373,7 @@ static void recSUB_(int info) { // D might equal T // xMOV(eax, ptr32[&cpuRegs.GPR.r[_Rs_].UL[0]]); - armLoad(EAX, PTR_CPU(GPR.r[_Rs_].UL[0])); + armLoad(EAX, PTR_CPU(cpuRegs.GPR.r[_Rs_].UL[0])); // xSUB(eax, xRegister32(EEREC_T)); armAsm->Sub(EAX, EAX, a64::WRegister(EEREC_T)); // xMOVSX(xRegister64(EEREC_D), eax); @@ -382,9 +382,9 @@ static void recSUB_(int info) else { // xMOV(xRegister32(EEREC_D), ptr32[&cpuRegs.GPR.r[_Rs_].UL[0]]); - armLoad(reg32, PTR_CPU(GPR.r[_Rs_].UL[0])); + armLoad(reg32, PTR_CPU(cpuRegs.GPR.r[_Rs_].UL[0])); // xSUB(xRegister32(EEREC_D), ptr32[&cpuRegs.GPR.r[_Rt_].UL[0]]); - armAsm->Sub(reg32, reg32, armLoad(PTR_CPU(GPR.r[_Rt_].UL[0]))); + armAsm->Sub(reg32, reg32, armLoad(PTR_CPU(cpuRegs.GPR.r[_Rt_].UL[0]))); // xMOVSX(xRegister64(EEREC_D), xRegister32(EEREC_D)); armAsm->Sxtw(a64::XRegister(EEREC_D), reg32); } @@ -420,7 +420,7 @@ static void recDSUB_consts(int info) } else { // xSUB(regd, ptr64[&cpuRegs.GPR.r[_Rt_].SD[0]]); - armAsm->Sub(regd, regd, armLoad64(PTR_CPU(GPR.r[_Rt_].SD[0]))); + armAsm->Sub(regd, regd, armLoad64(PTR_CPU(cpuRegs.GPR.r[_Rt_].SD[0]))); } // emitter will eliminate redundant moves. @@ -469,14 +469,14 @@ static void recDSUB_(int info) // xMOV(xRegister64(EEREC_D), xRegister64(EEREC_S)); armAsm->Mov(a64::XRegister(EEREC_D), a64::XRegister(EEREC_S)); // xSUB(xRegister64(EEREC_D), ptr64[&cpuRegs.GPR.r[_Rt_].UD[0]]); - armAsm->Sub(a64::XRegister(EEREC_D), a64::XRegister(EEREC_D), armLoad64(PTR_CPU(GPR.r[_Rt_].UD[0]))); + armAsm->Sub(a64::XRegister(EEREC_D), a64::XRegister(EEREC_D), armLoad64(PTR_CPU(cpuRegs.GPR.r[_Rt_].UD[0]))); } else if (info & PROCESS_EE_T) { // D might equal T const a64::XRegister regd(EEREC_D == EEREC_T ? RAX.GetCode() : EEREC_D); // xMOV(regd, ptr64[&cpuRegs.GPR.r[_Rs_].UD[0]]); - armLoad(regd, PTR_CPU(GPR.r[_Rs_].UD[0])); + armLoad(regd, PTR_CPU(cpuRegs.GPR.r[_Rs_].UD[0])); // xSUB(regd, xRegister64(EEREC_T)); armAsm->Sub(regd, regd, a64::XRegister(EEREC_T)); // xMOV(xRegister64(EEREC_D), regd); @@ -485,9 +485,9 @@ static void recDSUB_(int info) else { // xMOV(xRegister64(EEREC_D), ptr64[&cpuRegs.GPR.r[_Rs_].UD[0]]); - armLoad(a64::XRegister(EEREC_D), PTR_CPU(GPR.r[_Rs_].UD[0])); + armLoad(a64::XRegister(EEREC_D), PTR_CPU(cpuRegs.GPR.r[_Rs_].UD[0])); // xSUB(xRegister64(EEREC_D), ptr64[&cpuRegs.GPR.r[_Rt_].UD[0]]); - armAsm->Sub(a64::XRegister(EEREC_D), a64::XRegister(EEREC_D), armLoad64(PTR_CPU(GPR.r[_Rt_].UD[0]))); + armAsm->Sub(a64::XRegister(EEREC_D), a64::XRegister(EEREC_D), armLoad64(PTR_CPU(cpuRegs.GPR.r[_Rt_].UD[0]))); } } @@ -568,7 +568,7 @@ static void recLogicalOp_constv(LogicalOp op, int info, int creg, u32 vreg, int } else { // xMOV(xRegister64(EEREC_D), ptr64[&cpuRegs.GPR.r[vreg].UD[0]]); - armLoad(reg64, PTR_CPU(GPR.r[vreg].UD[0])); + armLoad(reg64, PTR_CPU(cpuRegs.GPR.r[vreg].UD[0])); } if (cval.SD[0] != identityInput) { // xImm64Op(xOP, xRegister64(EEREC_D), rax, cval.UD[0]); @@ -634,7 +634,7 @@ static void recLogicalOp(LogicalOp op, int info) } else { // xMOV(xRegister64(EEREC_D), ptr64[&cpuRegs.GPR.r[rs].UD[0]]); - armLoad(reg64, PTR_CPU(GPR.r[rs].UD[0])); + armLoad(reg64, PTR_CPU(cpuRegs.GPR.r[rs].UD[0])); } if (regt >= 0) { @@ -659,13 +659,13 @@ static void recLogicalOp(LogicalOp op, int info) switch (xOP) { case LogicalOp::AND: - armAsm->And(reg64, reg64, armLoad64(PTR_CPU(GPR.r[rt].UD[0]))); + armAsm->And(reg64, reg64, armLoad64(PTR_CPU(cpuRegs.GPR.r[rt].UD[0]))); break; case LogicalOp::NOR: case LogicalOp::OR: - armAsm->Orr(reg64, reg64, armLoad64(PTR_CPU(GPR.r[rt].UD[0]))); + armAsm->Orr(reg64, reg64, armLoad64(PTR_CPU(cpuRegs.GPR.r[rt].UD[0]))); break; case LogicalOp::XOR: - armAsm->Eor(reg64, reg64, armLoad64(PTR_CPU(GPR.r[rt].UD[0]))); + armAsm->Eor(reg64, reg64, armLoad64(PTR_CPU(cpuRegs.GPR.r[rt].UD[0]))); break; case LogicalOp::BAD: break; @@ -799,7 +799,7 @@ static void recSLTs_const(int info, int sign, int st) } else { // xImm64Op(xCMP, ptr64[&cpuRegs.GPR.r[st ? _Rs_ : _Rt_].UD[0]], rcx, cval); - armAsm->Cmp(armLoad64(PTR_CPU(GPR.r[st ? _Rs_ : _Rt_].UD[0])), cval); + armAsm->Cmp(armLoad64(PTR_CPU(cpuRegs.GPR.r[st ? _Rs_ : _Rt_].UD[0])), cval); } // SET(xRegister8(dreg)); armAsm->Cset(dreg, SET); @@ -832,7 +832,7 @@ static void recSLTs_(int info, int sign) } else { // xCMP(xRegister64(regs), ptr64[&cpuRegs.GPR.r[_Rt_].UD[0]]); - armAsm->Cmp(a64::XRegister(regs), armLoad64(PTR_CPU(GPR.r[_Rt_].UD[0]))); + armAsm->Cmp(a64::XRegister(regs), armLoad64(PTR_CPU(cpuRegs.GPR.r[_Rt_].UD[0]))); } // SET(xRegister8(dreg)); diff --git a/app/src/main/cpp/pcsx2/x86/ix86-32/iR5900AritImm.cpp b/app/src/main/cpp/pcsx2/x86/ix86-32/iR5900AritImm.cpp index bf9c9be..e9bf48d 100644 --- a/app/src/main/cpp/pcsx2/x86/ix86-32/iR5900AritImm.cpp +++ b/app/src/main/cpp/pcsx2/x86/ix86-32/iR5900AritImm.cpp @@ -41,7 +41,7 @@ static void recMoveStoT(int info) } else { // xMOV(xRegister32(EEREC_T), ptr32[&cpuRegs.GPR.r[_Rs_].UL[0]]); - armLoad(a64::WRegister(EEREC_T), PTR_CPU(GPR.r[_Rs_].UL[0])); + armLoad(a64::WRegister(EEREC_T), PTR_CPU(cpuRegs.GPR.r[_Rs_].UL[0])); } } @@ -53,7 +53,7 @@ static void recMoveStoT64(int info) } else { // xMOV(xRegister64(EEREC_T), ptr64[&cpuRegs.GPR.r[_Rs_].UD[0]]); - armLoad(a64::XRegister(EEREC_T), PTR_CPU(GPR.r[_Rs_].UD[0])); + armLoad(a64::XRegister(EEREC_T), PTR_CPU(cpuRegs.GPR.r[_Rs_].UD[0])); } } @@ -124,7 +124,7 @@ static void recSLTIU_(int info) } else { // xCMP(ptr64[&cpuRegs.GPR.r[_Rs_].UD[0]], _Imm_); - armAsm->Cmp(armLoad64(PTR_CPU(GPR.r[_Rs_].UD[0])), _Imm_); + armAsm->Cmp(armLoad64(PTR_CPU(cpuRegs.GPR.r[_Rs_].UD[0])), _Imm_); } // xSETB(xRegister8(dreg)); @@ -157,7 +157,7 @@ static void recSLTI_(int info) } else { // xCMP(ptr64[&cpuRegs.GPR.r[_Rs_].UD[0]], _Imm_); - armAsm->Cmp(armLoad64(PTR_CPU(GPR.r[_Rs_].UD[0])), _Imm_); + armAsm->Cmp(armLoad64(PTR_CPU(cpuRegs.GPR.r[_Rs_].UD[0])), _Imm_); } // xSETL(xRegister8(dreg)); diff --git a/app/src/main/cpp/pcsx2/x86/ix86-32/iR5900Branch.cpp b/app/src/main/cpp/pcsx2/x86/ix86-32/iR5900Branch.cpp index aba64e8..d48e485 100644 --- a/app/src/main/cpp/pcsx2/x86/ix86-32/iR5900Branch.cpp +++ b/app/src/main/cpp/pcsx2/x86/ix86-32/iR5900Branch.cpp @@ -55,7 +55,7 @@ static void recSetBranchEQ(int bne, int process, a64::Label *pj32Ptr) } else { // xImm64Op(xCMP, ptr64[&cpuRegs.GPR.r[_Rt_].UD[0]], rax, g_cpuConstRegs[_Rs_].UD[0]); - armAsm->Cmp(armLoad64(PTR_CPU(GPR.r[_Rt_].UD[0])), g_cpuConstRegs[_Rs_].UD[0]); + armAsm->Cmp(armLoad64(PTR_CPU(cpuRegs.GPR.r[_Rt_].UD[0])), g_cpuConstRegs[_Rs_].UD[0]); } } else if (process & PROCESS_CONSTT) @@ -70,7 +70,7 @@ static void recSetBranchEQ(int bne, int process, a64::Label *pj32Ptr) } else { // xImm64Op(xCMP, ptr64[&cpuRegs.GPR.r[_Rs_].UD[0]], rax, g_cpuConstRegs[_Rt_].UD[0]); - armAsm->Cmp(armLoad64(PTR_CPU(GPR.r[_Rs_].UD[0])), g_cpuConstRegs[_Rt_].UD[0]); + armAsm->Cmp(armLoad64(PTR_CPU(cpuRegs.GPR.r[_Rs_].UD[0])), g_cpuConstRegs[_Rt_].UD[0]); } } else @@ -87,7 +87,7 @@ static void recSetBranchEQ(int bne, int process, a64::Label *pj32Ptr) } else { // xCMP(xRegister64(regs), ptr64[&cpuRegs.GPR.r[_Rt_]]); - armAsm->Cmp(a64::XRegister(regs), armLoad64(PTR_CPU(GPR.r[_Rt_]))); + armAsm->Cmp(a64::XRegister(regs), armLoad64(PTR_CPU(cpuRegs.GPR.r[_Rt_]))); } } @@ -132,7 +132,7 @@ static void recSetBranchL(int ltz, a64::Label *pj32Ptr) } else { // xCMP(ptr64[&cpuRegs.GPR.r[_Rs_].UD[0]], 0); - armAsm->Cmp(armLoad64(PTR_CPU(GPR.r[_Rs_].UD[0])), 0); + armAsm->Cmp(armLoad64(PTR_CPU(cpuRegs.GPR.r[_Rs_].UD[0])), 0); } if (ltz) { @@ -397,7 +397,7 @@ void recBLTZAL() // xMOV64(rax, pc + 4); armAsm->Mov(RAX, pc + 4); // xMOV(ptr64[&cpuRegs.GPR.n.ra.UD[0]], rax); - armStore(PTR_CPU(GPR.n.ra.UD[0]), RAX); + armStore(PTR_CPU(cpuRegs.GPR.n.ra.UD[0]), RAX); if (GPR_IS_CONST1(_Rs_)) { @@ -450,7 +450,7 @@ void recBGEZAL() // xMOV64(rax, pc + 4); armAsm->Mov(RAX, pc + 4); // xMOV(ptr64[&cpuRegs.GPR.n.ra.UD[0]], rax); - armStore(PTR_CPU(GPR.n.ra.UD[0]), RAX); + armStore(PTR_CPU(cpuRegs.GPR.n.ra.UD[0]), RAX); if (GPR_IS_CONST1(_Rs_)) { @@ -503,7 +503,7 @@ void recBLTZALL() // xMOV64(rax, pc + 4); armAsm->Mov(RAX, pc + 4); // xMOV(ptr64[&cpuRegs.GPR.n.ra.UD[0]], rax); - armStore(PTR_CPU(GPR.n.ra.UD[0]), RAX); + armStore(PTR_CPU(cpuRegs.GPR.n.ra.UD[0]), RAX); if (GPR_IS_CONST1(_Rs_)) { @@ -545,7 +545,7 @@ void recBGEZALL() // xMOV64(rax, pc + 4); armAsm->Mov(RAX, pc + 4); // xMOV(ptr64[&cpuRegs.GPR.n.ra.UD[0]], rax); - armStore(PTR_CPU(GPR.n.ra.UD[0]), RAX); + armStore(PTR_CPU(cpuRegs.GPR.n.ra.UD[0]), RAX); if (GPR_IS_CONST1(_Rs_)) { @@ -600,7 +600,7 @@ void recBLEZ() armAsm->Cmp(a64::XRegister(regs), 0); else // xCMP(ptr64[&cpuRegs.GPR.r[_Rs_].UD[0]], 0); - armAsm->Cmp(armLoad64(PTR_CPU(GPR.r[_Rs_].UD[0])), 0); + armAsm->Cmp(armLoad64(PTR_CPU(cpuRegs.GPR.r[_Rs_].UD[0])), 0); // j32Ptr[0] = JG32(0); a64::Label j32Ptr; @@ -655,7 +655,7 @@ void recBGTZ() } else { // xCMP(ptr64[&cpuRegs.GPR.r[_Rs_].UD[0]], 0); - armAsm->Cmp(armLoad64(PTR_CPU(GPR.r[_Rs_].UD[0])), 0); + armAsm->Cmp(armLoad64(PTR_CPU(cpuRegs.GPR.r[_Rs_].UD[0])), 0); } // j32Ptr[0] = JLE32(0); @@ -880,7 +880,7 @@ void recBLEZL() } else { // xCMP(ptr64[&cpuRegs.GPR.r[_Rs_].UD[0]], 0); - armAsm->Cmp(armLoad64(PTR_CPU(GPR.r[_Rs_].UD[0])), 0); + armAsm->Cmp(armLoad64(PTR_CPU(cpuRegs.GPR.r[_Rs_].UD[0])), 0); } // j32Ptr[0] = JG32(0); @@ -927,7 +927,7 @@ void recBGTZL() } else { // xCMP(ptr64[&cpuRegs.GPR.r[_Rs_].UD[0]], 0); - armAsm->Cmp(armLoad64(PTR_CPU(GPR.r[_Rs_].UD[0])), 0); + armAsm->Cmp(armLoad64(PTR_CPU(cpuRegs.GPR.r[_Rs_].UD[0])), 0); } // j32Ptr[0] = JLE32(0); diff --git a/app/src/main/cpp/pcsx2/x86/ix86-32/iR5900Jump.cpp b/app/src/main/cpp/pcsx2/x86/ix86-32/iR5900Jump.cpp index bf89f33..94a6c72 100644 --- a/app/src/main/cpp/pcsx2/x86/ix86-32/iR5900Jump.cpp +++ b/app/src/main/cpp/pcsx2/x86/ix86-32/iR5900Jump.cpp @@ -57,9 +57,9 @@ void recJAL() else { // xMOV(ptr32[&cpuRegs.GPR.r[31].UL[0]], pc + 4); - armStore(PTR_CPU(GPR.r[31].UL[0]), pc + 4); + armStore(PTR_CPU(cpuRegs.GPR.r[31].UL[0]), pc + 4); // xMOV(ptr32[&cpuRegs.GPR.r[31].UL[1]], 0); - armStore(PTR_CPU(GPR.r[31].UL[1]), 0); + armStore(PTR_CPU(cpuRegs.GPR.r[31].UL[1]), 0); } recompileNextInstruction(true, false); @@ -135,7 +135,7 @@ void recJALR() else { // xWriteImm64ToMem(&cpuRegs.GPR.r[_Rd_].UD[0], rax, newpc); - armStore64(PTR_CPU(GPR.r[_Rd_].UD[0]), newpc); + armStore64(PTR_CPU(cpuRegs.GPR.r[_Rd_].UD[0]), newpc); } } @@ -147,15 +147,15 @@ void recJALR() if (x86regs[wbreg].inuse && x86regs[wbreg].type == X86TYPE_PCWRITEBACK) { // xMOV(ptr[&cpuRegs.pc], xRegister32(wbreg)); - armStore(PTR_CPU(pc), a64::WRegister(wbreg)); + armStore(PTR_CPU(cpuRegs.pc), a64::WRegister(wbreg)); x86regs[wbreg].inuse = 0; } else { // xMOV(eax, ptr[&cpuRegs.pcWriteback]); - armLoad(EAX, PTR_CPU(pcWriteback)); + armLoad(EAX, PTR_CPU(cpuRegs.pcWriteback)); // xMOV(ptr[&cpuRegs.pc], eax); - armStore(PTR_CPU(pc), EAX); + armStore(PTR_CPU(cpuRegs.pc), EAX); } } else @@ -164,7 +164,7 @@ void recJALR() { const int x86reg = _allocX86reg(X86TYPE_GPR, _Rs_, MODE_READ); // xMOV(ptr32[&cpuRegs.pc], xRegister32(x86reg)); - armStore(PTR_CPU(pc), a64::WRegister(x86reg)); + armStore(PTR_CPU(cpuRegs.pc), a64::WRegister(x86reg)); } else { diff --git a/app/src/main/cpp/pcsx2/x86/ix86-32/iR5900Move.cpp b/app/src/main/cpp/pcsx2/x86/ix86-32/iR5900Move.cpp index f636ece..04e4710 100644 --- a/app/src/main/cpp/pcsx2/x86/ix86-32/iR5900Move.cpp +++ b/app/src/main/cpp/pcsx2/x86/ix86-32/iR5900Move.cpp @@ -102,7 +102,7 @@ static void recMFHILO(bool hi, bool upper) else { // xPINSR.Q(xRegisterSSE(xmmd), ptr64[hi ? &cpuRegs.HI.UD[static_cast(upper)] // : &cpuRegs.LO.UD[static_cast(upper)]], 0); - armLoad(REX, hi ? PTR_CPU(HI.UD[static_cast(upper)]) : PTR_CPU(LO.UD[static_cast(upper)])); + armLoad(REX, hi ? PTR_CPU(cpuRegs.HI.UD[static_cast(upper)]) : PTR_CPU(cpuRegs.LO.UD[static_cast(upper)])); armAsm->Ins(a64::QRegister(xmmd).V2D(), 0, REX); } } @@ -133,11 +133,11 @@ static void recMFHILO(bool hi, bool upper) if (upper) { // xPEXTR.Q(ptr64[&cpuRegs.GPR.r[_Rd_].UD[0]], xRegisterSSE(xmmhilo), 1); armAsm->Fmov(REX, a64::QRegister(xmmhilo).V1D(), 1); - armStore(PTR_CPU(GPR.r[_Rd_].UD[0]), REX); + armStore(PTR_CPU(cpuRegs.GPR.r[_Rd_].UD[0]), REX); } else { // xMOVQ(ptr64[&cpuRegs.GPR.r[_Rd_].UD[0]], xRegisterSSE(xmmhilo)); - armStore(PTR_CPU(GPR.r[_Rd_].UD[0]), a64::QRegister(xmmhilo).V1D()); + armStore(PTR_CPU(cpuRegs.GPR.r[_Rd_].UD[0]), a64::QRegister(xmmhilo).V1D()); } } else if (gprd >= 0) @@ -149,20 +149,20 @@ static void recMFHILO(bool hi, bool upper) else { // xMOV(xRegister64(gprd), ptr64[hi ? &cpuRegs.HI.UD[static_cast(upper)] // : &cpuRegs.LO.UD[static_cast(upper)]]); - armLoad(a64::XRegister(gprd), hi ? PTR_CPU(HI.UD[static_cast(upper)]) : PTR_CPU(LO.UD[static_cast(upper)])); + armLoad(a64::XRegister(gprd), hi ? PTR_CPU(cpuRegs.HI.UD[static_cast(upper)]) : PTR_CPU(cpuRegs.LO.UD[static_cast(upper)])); } } else if (gprreg >= 0) { // xMOV(ptr64[&cpuRegs.GPR.r[_Rd_].UD[0]], xRegister64(gprreg)); - armStore(PTR_CPU(GPR.r[_Rd_].UD[0]), a64::XRegister(gprreg)); + armStore(PTR_CPU(cpuRegs.GPR.r[_Rd_].UD[0]), a64::XRegister(gprreg)); } else { // xMOV(rax, ptr64[hi ? &cpuRegs.HI.UD[static_cast(upper)] : &cpuRegs.LO.UD[static_cast(upper)]]); - armLoad(RAX, hi ? PTR_CPU(HI.UD[static_cast(upper)]) : PTR_CPU(LO.UD[static_cast(upper)])); + armLoad(RAX, hi ? PTR_CPU(cpuRegs.HI.UD[static_cast(upper)]) : PTR_CPU(cpuRegs.LO.UD[static_cast(upper)])); // xMOV(ptr64[&cpuRegs.GPR.r[_Rd_].UD[0]], rax); - armStore(PTR_CPU(GPR.r[_Rd_].UD[0]), RAX); + armStore(PTR_CPU(cpuRegs.GPR.r[_Rd_].UD[0]), RAX); } } } @@ -197,7 +197,7 @@ static void recMTHILO(bool hi, bool upper) else { // xMOVQ(ptr64[hi ? &cpuRegs.HI.UD[static_cast(upper)] // : &cpuRegs.LO.UD[static_cast(upper)]], xRegisterSSE(xmms)); - armStore(hi ? PTR_CPU(HI.UD[static_cast(upper)]) : PTR_CPU(LO.UD[static_cast(upper)]), a64::QRegister(xmms).V1D()); + armStore(hi ? PTR_CPU(cpuRegs.HI.UD[static_cast(upper)]) : PTR_CPU(cpuRegs.LO.UD[static_cast(upper)]), a64::QRegister(xmms).V1D()); } } } @@ -222,7 +222,7 @@ static void recMTHILO(bool hi, bool upper) else { // xPINSR.Q(xRegisterSSE(xmmhilo), ptr64[&cpuRegs.GPR.r[_Rs_].UD[0]], static_cast(upper)); - armAsm->Ins(a64::QRegister(xmmhilo).V2D(), static_cast(upper), armLoad64(PTR_CPU(GPR.r[_Rs_].UD[0]))); + armAsm->Ins(a64::QRegister(xmmhilo).V2D(), static_cast(upper), armLoad64(PTR_CPU(cpuRegs.GPR.r[_Rs_].UD[0]))); } } else @@ -241,7 +241,7 @@ static void recMTHILO(bool hi, bool upper) // force into a register, since we need to load it to write anyway gprs = _allocX86reg(X86TYPE_GPR, _Rs_, MODE_READ); // xMOV(ptr64[hi ? &cpuRegs.HI.UD[static_cast(upper)] : &cpuRegs.LO.UD[static_cast(upper)]], xRegister64(gprs)); - armStore(hi ? PTR_CPU(HI.UD[static_cast(upper)]) : PTR_CPU(LO.UD[static_cast(upper)]), a64::XRegister(gprs)); + armStore(hi ? PTR_CPU(cpuRegs.HI.UD[static_cast(upper)]) : PTR_CPU(cpuRegs.LO.UD[static_cast(upper)]), a64::XRegister(gprs)); } } } @@ -313,7 +313,7 @@ static void recMOVZtemp_consts(int info) } else { // xCMP(ptr64[&cpuRegs.GPR.r[_Rt_].UD[0]], 0); - armAsm->Cmp(armLoad64(PTR_CPU(GPR.r[_Rt_].UD[0])), 0); + armAsm->Cmp(armLoad64(PTR_CPU(cpuRegs.GPR.r[_Rt_].UD[0])), 0); } // xCMOVE(xRegister64(EEREC_D), xRegister64(regs)); @@ -329,7 +329,7 @@ static void recMOVZtemp_constt(int info) } else { // xMOV(xRegister64(EEREC_D), ptr64[&cpuRegs.GPR.r[_Rs_].UD[0]]); - armLoad(a64::XRegister(EEREC_D), PTR_CPU(GPR.r[_Rs_].UD[0])); + armLoad(a64::XRegister(EEREC_D), PTR_CPU(cpuRegs.GPR.r[_Rs_].UD[0])); } } @@ -341,7 +341,7 @@ static void recMOVZtemp_(int info) } else { // xCMP(ptr64[&cpuRegs.GPR.r[_Rt_].UD[0]], 0); - armAsm->Cmp(armLoad64(PTR_CPU(GPR.r[_Rt_].UD[0])), 0); + armAsm->Cmp(armLoad64(PTR_CPU(cpuRegs.GPR.r[_Rt_].UD[0])), 0); } auto reg64 = a64::XRegister(EEREC_D); @@ -351,7 +351,7 @@ static void recMOVZtemp_(int info) } else { // xCMOVE(xRegister64(EEREC_D), ptr64[&cpuRegs.GPR.r[_Rs_].UD[0]]); - armAsm->Csel(reg64, armLoad64(PTR_CPU(GPR.r[_Rs_].UD[0])), reg64, a64::Condition::eq); + armAsm->Csel(reg64, armLoad64(PTR_CPU(cpuRegs.GPR.r[_Rs_].UD[0])), reg64, a64::Condition::eq); } } @@ -385,7 +385,7 @@ static void recMOVNtemp_consts(int info) } else { // xCMP(ptr64[&cpuRegs.GPR.r[_Rt_].UD[0]], 0); - armAsm->Cmp(armLoad64(PTR_CPU(GPR.r[_Rt_].UD[0])), 0); + armAsm->Cmp(armLoad64(PTR_CPU(cpuRegs.GPR.r[_Rt_].UD[0])), 0); } // xCMOVNE(xRegister64(EEREC_D), xRegister64(regs)); @@ -401,7 +401,7 @@ static void recMOVNtemp_constt(int info) } else { // xMOV(xRegister64(EEREC_D), ptr64[&cpuRegs.GPR.r[_Rs_].UD[0]]); - armLoad(a64::XRegister(EEREC_D), PTR_CPU(GPR.r[_Rs_].UD[0])); + armLoad(a64::XRegister(EEREC_D), PTR_CPU(cpuRegs.GPR.r[_Rs_].UD[0])); } } @@ -413,7 +413,7 @@ static void recMOVNtemp_(int info) } else { // xCMP(ptr64[&cpuRegs.GPR.r[_Rt_].UD[0]], 0); - armAsm->Cmp(armLoad64(PTR_CPU(GPR.r[_Rt_].UD[0])), 0); + armAsm->Cmp(armLoad64(PTR_CPU(cpuRegs.GPR.r[_Rt_].UD[0])), 0); } auto reg64 = a64::XRegister(EEREC_D); @@ -423,7 +423,7 @@ static void recMOVNtemp_(int info) } else { // xCMOVNE(xRegister64(EEREC_D), ptr64[&cpuRegs.GPR.r[_Rs_].UD[0]]); - armAsm->Csel(reg64, armLoad64(PTR_CPU(GPR.r[_Rs_].UD[0])), reg64, a64::Condition::ne); + armAsm->Csel(reg64, armLoad64(PTR_CPU(cpuRegs.GPR.r[_Rs_].UD[0])), reg64, a64::Condition::ne); } } diff --git a/app/src/main/cpp/pcsx2/x86/ix86-32/iR5900MultDiv.cpp b/app/src/main/cpp/pcsx2/x86/ix86-32/iR5900MultDiv.cpp index fc8c60e..e8a234e 100644 --- a/app/src/main/cpp/pcsx2/x86/ix86-32/iR5900MultDiv.cpp +++ b/app/src/main/cpp/pcsx2/x86/ix86-32/iR5900MultDiv.cpp @@ -75,7 +75,7 @@ static void recWritebackHILO(int info, bool writed, bool upper) armAsm->Sxtw(RAX, EAX); eax_sign_extended = true; // xMOV(ptr64[&cpuRegs.LO.UD[upper]], rax); - armStore(PTR_CPU(LO.UD[upper]), RAX); + armStore(PTR_CPU(cpuRegs.LO.UD[upper]), RAX); } } } @@ -105,7 +105,7 @@ static void recWritebackHILO(int info, bool writed, bool upper) // xMOVSX(rdx, edx); armAsm->Sxtw(RDX, EDX); // xMOV(ptr64[&cpuRegs.HI.UD[upper]], rdx); - armStore(PTR_CPU(HI.UD[upper]), RDX); + armStore(PTR_CPU(cpuRegs.HI.UD[upper]), RDX); } } } @@ -133,7 +133,7 @@ static void recWritebackHILO(int info, bool writed, bool upper) armAsm->Sxtw(RAX, EAX); } // xMOV(ptr64[&cpuRegs.GPR.r[_Rd_].UD[0]], rax); - armStore(PTR_CPU(GPR.r[_Rd_].UD[0]), RAX); + armStore(PTR_CPU(cpuRegs.GPR.r[_Rd_].UD[0]), RAX); } } } @@ -168,7 +168,7 @@ static void recWritebackConstHILO(u64 res, bool writed, int upper) } else { // xImm64Op(xMOV, ptr64[&cpuRegs.LO.UD[upper]], rax, loval); - armStore64(PTR_CPU(LO.UD[upper]), loval); + armStore64(PTR_CPU(cpuRegs.LO.UD[upper]), loval); } } } @@ -194,7 +194,7 @@ static void recWritebackConstHILO(u64 res, bool writed, int upper) } else { // xImm64Op(xMOV, ptr64[&cpuRegs.HI.UD[upper]], rax, hival); - armStore64(PTR_CPU(HI.UD[upper]), hival); + armStore64(PTR_CPU(cpuRegs.HI.UD[upper]), hival); } } } @@ -211,7 +211,7 @@ static void recWritebackConstHILO(u64 res, bool writed, int upper) } else { // xImm64Op(xMOV, ptr64[&cpuRegs.GPR.r[_Rd_].UD[0]], rax, loval); - armStore64(PTR_CPU(GPR.r[_Rd_].UD[0]), loval); + armStore64(PTR_CPU(cpuRegs.GPR.r[_Rd_].UD[0]), loval); } } } @@ -238,7 +238,7 @@ static void recMULTsuper(int info, bool sign, bool upper, int process) else { // sign ? xMUL(ptr32[&cpuRegs.GPR.r[_Rt_].UL[0]]) : xUMUL( // ptr32[&cpuRegs.GPR.r[_Rt_].UL[0]]); - armLoad(EEX, PTR_CPU(GPR.r[_Rt_].UL[0])); + armLoad(EEX, PTR_CPU(cpuRegs.GPR.r[_Rt_].UL[0])); sign ? armAsm->Smull(RAX, EAX, EEX) : armAsm->Umull(RAX, EAX, EEX); } } @@ -253,7 +253,7 @@ static void recMULTsuper(int info, bool sign, bool upper, int process) else { // sign ? xMUL(ptr32[&cpuRegs.GPR.r[_Rs_].UL[0]]) : xUMUL( // ptr32[&cpuRegs.GPR.r[_Rs_].UL[0]]); - armLoad(EEX, PTR_CPU(GPR.r[_Rs_].UL[0])); + armLoad(EEX, PTR_CPU(cpuRegs.GPR.r[_Rs_].UL[0])); sign ? armAsm->Smull(RAX, EAX, EEX) : armAsm->Umull(RAX, EAX, EEX); } } @@ -266,7 +266,7 @@ static void recMULTsuper(int info, bool sign, bool upper, int process) } else { // xMOV(eax, ptr[&cpuRegs.GPR.r[_Rt_].UL[0]]); - armLoad(EAX, PTR_CPU(GPR.r[_Rt_].UL[0])); + armLoad(EAX, PTR_CPU(cpuRegs.GPR.r[_Rt_].UL[0])); } if (info & PROCESS_EE_S) { @@ -276,7 +276,7 @@ static void recMULTsuper(int info, bool sign, bool upper, int process) else { // sign ? xMUL(ptr32[&cpuRegs.GPR.r[_Rs_].UL[0]]) : xUMUL( // ptr32[&cpuRegs.GPR.r[_Rs_].UL[0]]); - armLoad(EEX, PTR_CPU(GPR.r[_Rs_].UL[0])); + armLoad(EEX, PTR_CPU(cpuRegs.GPR.r[_Rs_].UL[0])); sign ? armAsm->Smull(RAX, EAX, EEX) : armAsm->Umull(RAX, EAX, EEX); } } @@ -418,7 +418,7 @@ static void recDIVsuper(int info, bool sign, bool upper, int process) } else { // xMOV(divisor, ptr[&cpuRegs.GPR.r[_Rt_].UL[0]]); - armLoad(divisor, PTR_CPU(GPR.r[_Rt_].UL[0])); + armLoad(divisor, PTR_CPU(cpuRegs.GPR.r[_Rt_].UL[0])); } } @@ -626,15 +626,15 @@ static void writeBackMAddToHiLoRd(int hiloID) _eeOnWriteReg(_Rd_, 1); _deleteEEreg(_Rd_, 0); // xMOV(ptr[&cpuRegs.GPR.r[_Rd_].UD[0]], rax); - armStore(PTR_CPU(GPR.r[_Rd_].UD[0]), RAX); + armStore(PTR_CPU(cpuRegs.GPR.r[_Rd_].UD[0]), RAX); } // xMOV(ptr[&cpuRegs.LO.UD[hiloID]], rax); - armStore(PTR_CPU(LO.UD[hiloID]), RAX); + armStore(PTR_CPU(cpuRegs.LO.UD[hiloID]), RAX); // xMOVSX(rax, edx); armAsm->Sxtw(RAX, EDX); // xMOV(ptr[&cpuRegs.HI.UD[hiloID]], rax); - armStore(PTR_CPU(HI.UD[hiloID]), RAX); + armStore(PTR_CPU(cpuRegs.HI.UD[hiloID]), RAX); } static void addConstantAndWriteBackToHiLoRd(int hiloID, u64 constant) @@ -645,9 +645,9 @@ static void addConstantAndWriteBackToHiLoRd(int hiloID, u64 constant) _deleteEEreg(XMMGPR_HI, 1); // xMOV(eax, ptr[&cpuRegs.LO.UL[hiloID * 2]]); - armLoad(EAX, PTR_CPU(LO.UL[hiloID * 2])); + armLoad(EAX, PTR_CPU(cpuRegs.LO.UL[hiloID * 2])); // xMOV(ehi, ptr[&cpuRegs.HI.UL[hiloID * 2]]); - armLoad(ehi, PTR_CPU(HI.UL[hiloID * 2])); + armLoad(ehi, PTR_CPU(cpuRegs.HI.UL[hiloID * 2])); // xADD(eax, (u32)(constant & 0xffffffff)); armAsm->Add(EAX, EAX, (u32)(constant & 0xffffffff)); // xADC(ehi, (u32)(constant >> 32)); @@ -658,9 +658,9 @@ static void addConstantAndWriteBackToHiLoRd(int hiloID, u64 constant) static void addEaxEdxAndWriteBackToHiLoRd(int hiloID) { // xADD(eax, ptr[&cpuRegs.LO.UL[hiloID * 2]]); - armAsm->Add(EAX, EAX, armLoad(PTR_CPU(LO.UL[hiloID * 2]))); + armAsm->Add(EAX, EAX, armLoad(PTR_CPU(cpuRegs.LO.UL[hiloID * 2]))); // xADC(edx, ptr[&cpuRegs.HI.UL[hiloID * 2]]); - armAsm->Adc(EDX, EDX, armLoad(PTR_CPU(HI.UL[hiloID * 2]))); + armAsm->Adc(EDX, EDX, armLoad(PTR_CPU(cpuRegs.HI.UL[hiloID * 2]))); writeBackMAddToHiLoRd(hiloID); } @@ -686,21 +686,21 @@ void recMADD() // xMOV(eax, g_cpuConstRegs[_Rs_].UL[0]); armAsm->Mov(EAX, g_cpuConstRegs[_Rs_].UL[0]); // xMUL(ptr32[&cpuRegs.GPR.r[_Rt_].UL[0]]); - armAsm->Smull(RAX, EAX, armLoad(PTR_CPU(GPR.r[_Rt_].UL[0]))); + armAsm->Smull(RAX, EAX, armLoad(PTR_CPU(cpuRegs.GPR.r[_Rt_].UL[0]))); } else if (GPR_IS_CONST1(_Rt_)) { // xMOV(eax, g_cpuConstRegs[_Rt_].UL[0]); armAsm->Mov(EAX, g_cpuConstRegs[_Rt_].UL[0]); // xMUL(ptr32[&cpuRegs.GPR.r[_Rs_].UL[0]]); - armAsm->Smull(RAX, EAX, armLoad(PTR_CPU(GPR.r[_Rs_].UL[0]))); + armAsm->Smull(RAX, EAX, armLoad(PTR_CPU(cpuRegs.GPR.r[_Rs_].UL[0]))); } else { // xMOV(eax, ptr[&cpuRegs.GPR.r[_Rs_].UL[0]]); - armLoad(EAX, PTR_CPU(GPR.r[_Rs_].UL[0])); + armLoad(EAX, PTR_CPU(cpuRegs.GPR.r[_Rs_].UL[0])); // xMUL(ptr32[&cpuRegs.GPR.r[_Rt_].UL[0]]); - armAsm->Smull(RAX, EAX, armLoad(PTR_CPU(GPR.r[_Rt_].UL[0]))); + armAsm->Smull(RAX, EAX, armLoad(PTR_CPU(cpuRegs.GPR.r[_Rt_].UL[0]))); } armAsm->Lsr(RDX, RAX, 32); @@ -728,21 +728,21 @@ void recMADDU() // xMOV(eax, g_cpuConstRegs[_Rs_].UL[0]); armAsm->Mov(EAX, g_cpuConstRegs[_Rs_].UL[0]); // xUMUL(ptr32[&cpuRegs.GPR.r[_Rt_].UL[0]]); - armAsm->Umull(RAX, EAX, armLoad(PTR_CPU(GPR.r[_Rt_].UL[0]))); + armAsm->Umull(RAX, EAX, armLoad(PTR_CPU(cpuRegs.GPR.r[_Rt_].UL[0]))); } else if (GPR_IS_CONST1(_Rt_)) { // xMOV(eax, g_cpuConstRegs[_Rt_].UL[0]); armAsm->Mov(EAX, g_cpuConstRegs[_Rt_].UL[0]); // xUMUL(ptr32[&cpuRegs.GPR.r[_Rs_].UL[0]]); - armAsm->Umull(RAX, EAX, armLoad(PTR_CPU(GPR.r[_Rs_].UL[0]))); + armAsm->Umull(RAX, EAX, armLoad(PTR_CPU(cpuRegs.GPR.r[_Rs_].UL[0]))); } else { // xMOV(eax, ptr[&cpuRegs.GPR.r[_Rs_].UL[0]]); - armLoad(EAX, PTR_CPU(GPR.r[_Rs_].UL[0])); + armLoad(EAX, PTR_CPU(cpuRegs.GPR.r[_Rs_].UL[0])); // xUMUL(ptr32[&cpuRegs.GPR.r[_Rt_].UL[0]]); - armAsm->Umull(RAX, EAX, armLoad(PTR_CPU(GPR.r[_Rt_].UL[0]))); + armAsm->Umull(RAX, EAX, armLoad(PTR_CPU(cpuRegs.GPR.r[_Rt_].UL[0]))); } armAsm->Lsr(RDX, RAX, 32); @@ -770,21 +770,21 @@ void recMADD1() // xMOV(eax, g_cpuConstRegs[_Rs_].UL[0]); armAsm->Mov(EAX, g_cpuConstRegs[_Rs_].UL[0]); // xMUL(ptr32[&cpuRegs.GPR.r[_Rt_].UL[0]]); - armAsm->Smull(RAX, EAX, armLoad(PTR_CPU(GPR.r[_Rt_].UL[0]))); + armAsm->Smull(RAX, EAX, armLoad(PTR_CPU(cpuRegs.GPR.r[_Rt_].UL[0]))); } else if (GPR_IS_CONST1(_Rt_)) { // xMOV(eax, g_cpuConstRegs[_Rt_].UL[0]); armAsm->Mov(EAX, g_cpuConstRegs[_Rt_].UL[0]); // xMUL(ptr32[&cpuRegs.GPR.r[_Rs_].UL[0]]); - armAsm->Smull(RAX, EAX, armLoad(PTR_CPU(GPR.r[_Rs_].UL[0]))); + armAsm->Smull(RAX, EAX, armLoad(PTR_CPU(cpuRegs.GPR.r[_Rs_].UL[0]))); } else { // xMOV(eax, ptr[&cpuRegs.GPR.r[_Rs_].UL[0]]); - armLoad(EAX, PTR_CPU(GPR.r[_Rs_].UL[0])); + armLoad(EAX, PTR_CPU(cpuRegs.GPR.r[_Rs_].UL[0])); // xMUL(ptr32[&cpuRegs.GPR.r[_Rt_].UL[0]]); - armAsm->Smull(RAX, EAX, armLoad(PTR_CPU(GPR.r[_Rt_].UL[0]))); + armAsm->Smull(RAX, EAX, armLoad(PTR_CPU(cpuRegs.GPR.r[_Rt_].UL[0]))); } armAsm->Lsr(RDX, RAX, 32); @@ -812,21 +812,21 @@ void recMADDU1() // xMOV(eax, g_cpuConstRegs[_Rs_].UL[0]); armAsm->Mov(EAX, g_cpuConstRegs[_Rs_].UL[0]); // xUMUL(ptr32[&cpuRegs.GPR.r[_Rt_].UL[0]]); - armAsm->Umull(RAX, EAX, armLoad(PTR_CPU(GPR.r[_Rt_].UL[0]))); + armAsm->Umull(RAX, EAX, armLoad(PTR_CPU(cpuRegs.GPR.r[_Rt_].UL[0]))); } else if (GPR_IS_CONST1(_Rt_)) { // xMOV(eax, g_cpuConstRegs[_Rt_].UL[0]); armAsm->Mov(EAX, g_cpuConstRegs[_Rt_].UL[0]); // xUMUL(ptr32[&cpuRegs.GPR.r[_Rs_].UL[0]]); - armAsm->Umull(RAX, EAX, armLoad(PTR_CPU(GPR.r[_Rs_].UL[0]))); + armAsm->Umull(RAX, EAX, armLoad(PTR_CPU(cpuRegs.GPR.r[_Rs_].UL[0]))); } else { // xMOV(eax, ptr[&cpuRegs.GPR.r[_Rs_].UL[0]]); - armLoad(EAX, PTR_CPU(GPR.r[_Rs_].UL[0])); + armLoad(EAX, PTR_CPU(cpuRegs.GPR.r[_Rs_].UL[0])); // xUMUL(ptr32[&cpuRegs.GPR.r[_Rt_].UL[0]]); - armAsm->Umull(RAX, EAX, armLoad(PTR_CPU(GPR.r[_Rt_].UL[0]))); + armAsm->Umull(RAX, EAX, armLoad(PTR_CPU(cpuRegs.GPR.r[_Rt_].UL[0]))); } armAsm->Lsr(RDX, RAX, 32); diff --git a/app/src/main/cpp/pcsx2/x86/ix86-32/iR5900Shift.cpp b/app/src/main/cpp/pcsx2/x86/ix86-32/iR5900Shift.cpp index 0f983a8..accf128 100644 --- a/app/src/main/cpp/pcsx2/x86/ix86-32/iR5900Shift.cpp +++ b/app/src/main/cpp/pcsx2/x86/ix86-32/iR5900Shift.cpp @@ -48,7 +48,7 @@ static void recMoveTtoD(int info) } else { // xMOV(xRegister32(EEREC_D), ptr32[&cpuRegs.GPR.r[_Rt_].UL[0]]); - armLoad(reg32, PTR_CPU(GPR.r[_Rt_].UL[0])); + armLoad(reg32, PTR_CPU(cpuRegs.GPR.r[_Rt_].UL[0])); } } @@ -61,7 +61,7 @@ static void recMoveTtoD64(int info) } else { // xMOV(xRegister64(EEREC_D), ptr64[&cpuRegs.GPR.r[_Rt_].UD[0]]); - armLoad(reg64, PTR_CPU(GPR.r[_Rt_].UD[0])); + armLoad(reg64, PTR_CPU(cpuRegs.GPR.r[_Rt_].UD[0])); } } @@ -74,7 +74,7 @@ static void recMoveSToRCX(int info) } else { // xMOV(rcx, ptr64[&cpuRegs.GPR.r[_Rs_].UL[0]]); - armLoad(RCX, PTR_CPU(GPR.r[_Rs_].UL[0])); + armLoad(RCX, PTR_CPU(cpuRegs.GPR.r[_Rs_].UL[0])); } // armAsm->Uxth(RCX, RCX); } diff --git a/app/src/main/cpp/pcsx2/x86/microVU_Macro.inl b/app/src/main/cpp/pcsx2/x86/microVU_Macro.inl index 52cc743..36178fa 100644 --- a/app/src/main/cpp/pcsx2/x86/microVU_Macro.inl +++ b/app/src/main/cpp/pcsx2/x86/microVU_Macro.inl @@ -148,7 +148,7 @@ bool mVUIsReservedCOP2(int hostreg) void recV##f() \ { \ iFlushCall(FLUSH_FOR_POSSIBLE_MICRO_EXEC); \ - armAdd(PTR_CPU(cycle), scaleblockcycles_clear()); \ + armAdd(PTR_CPU(cpuRegs.cycle), scaleblockcycles_clear()); \ recCall(V##f); \ } @@ -360,7 +360,7 @@ static void COP2_Interlock(bool mBitSync) // xMOV(eax, ptr32[&cpuRegs.cycle]); // xADD(eax, scaleblockcycles_clear()); // xMOV(ptr32[&cpuRegs.cycle], eax); // update cycles - armAdd(EAX, PTR_CPU(cycle), scaleblockcycles_clear()); + armAdd(EAX, PTR_CPU(cpuRegs.cycle), scaleblockcycles_clear()); // xTEST(ptr32[&VU0.VI[REG_VPU_STAT].UL], 0x1); armAsm->Tst(armLoadPtr(PTR_VUR(VI[REG_VPU_STAT].UL)), 0x1); @@ -413,7 +413,7 @@ static void mVUSyncVU0() // xMOV(eax, ptr32[&cpuRegs.cycle]); // xADD(eax, scaleblockcycles_clear()); // xMOV(ptr32[&cpuRegs.cycle], eax); // update cycles - armAdd(EAX, PTR_CPU(cycle), scaleblockcycles_clear()); + armAdd(EAX, PTR_CPU(cpuRegs.cycle), scaleblockcycles_clear()); // xTEST(ptr32[&VU0.VI[REG_VPU_STAT].UL], 0x1); armAsm->Tst(armLoadPtr(PTR_VUR(VI[REG_VPU_STAT].UL)), 0x1); @@ -679,7 +679,7 @@ static void recCTC2() else { // xMOVZX(xRegister32(vireg), ptr16[&cpuRegs.GPR.r[_Rt_].US[0]]); - armLoadh(reg32, PTR_CPU(GPR.r[_Rt_].US[0])); + armLoadh(reg32, PTR_CPU(cpuRegs.GPR.r[_Rt_].US[0])); } } } @@ -743,7 +743,7 @@ static void recCTC2() } else { // xMOVSSZX(xRegisterSSE(xmmreg), ptr32[&cpuRegs.GPR.r[_Rt_].SD[0]]); - armLoad(regQ.S(), PTR_CPU(GPR.r[_Rt_].SD[0])); + armLoad(regQ.S(), PTR_CPU(cpuRegs.GPR.r[_Rt_].SD[0])); } // xSHUF.PS(xRegisterSSE(xmmreg), xRegisterSSE(xmmreg), 0); armSHUFPS(regQ, regQ, 0); @@ -794,7 +794,7 @@ static void recQMFC2() } else { // xMOVAPS(ptr128[&cpuRegs.GPR.r[_Rt_].UQ], xRegisterSSE(ftreg)); - armStore(PTR_CPU(GPR.r[_Rt_].UQ), a64::QRegister(ftreg).Q()); + armStore(PTR_CPU(cpuRegs.GPR.r[_Rt_].UQ), a64::QRegister(ftreg).Q()); } // don't cache vf00, microvu doesn't like it @@ -852,7 +852,7 @@ static void recQMTC2() } else { // xMOVAPS(xRegisterSSE(vfreg), ptr128[&cpuRegs.GPR.r[_Rt_].UQ]); - armLoad(a64::QRegister(vfreg).Q(), PTR_CPU(GPR.r[_Rt_].UQ)); + armLoad(a64::QRegister(vfreg).Q(), PTR_CPU(cpuRegs.GPR.r[_Rt_].UQ)); } } }