diff --git a/app/src/main/cpp/pcsx2/VUDef.h b/app/src/main/cpp/pcsx2/VUDef.h
index 763f3ce..b1e5f00 100644
--- a/app/src/main/cpp/pcsx2/VUDef.h
+++ b/app/src/main/cpp/pcsx2/VUDef.h
@@ -230,6 +230,11 @@ struct FPUd_Globals
     //u64		dlb_s_neg[2];
 };
 
+struct SSEMasks
+{
+    u32 MIN_MAX_1[4], MIN_MAX_2[4], ADD_SS[4];
+};
+
 struct mVU_SSE4
 {
     u32 sse4_minvals[2][4] = {
@@ -252,6 +257,12 @@ struct mVU_SSE4
     u32 g_minvals[4] = {0xff7fffff, 0xff7fffff, 0xff7fffff, 0xff7fffff};
     u32 g_maxvals[4] = {0x7f7fffff, 0x7f7fffff, 0x7f7fffff, 0x7f7fffff};
     ////
+    u32 minmax_mask[8] =
+    {
+        0xffffffff, 0x80000000, 0, 0,
+        0,          0x40000000, 0, 0,
+    };
+    ////
     FPUd_Globals s_const =
     {
         {0x80000000, 0xffffffff, 0xffffffff, 0xffffffff},
@@ -273,10 +284,11 @@ struct mVU_SSE4
         //{0x8000000000000000ULL, 0},
     };
     ////
-    u32 minmax_mask[8] =
+    SSEMasks sseMasks =
     {
-        0xffffffff, 0x80000000, 0, 0,
-        0,          0x40000000, 0, 0,
+        {0xffffffff, 0x80000000, 0xffffffff, 0x80000000},
+        {0x00000000, 0x40000000, 0x00000000, 0x40000000},
+        {0x80000000, 0xffffffff, 0xffffffff, 0xffffffff},
     };
 };
 
diff --git a/app/src/main/cpp/pcsx2/x86/microVU_Compile.inl b/app/src/main/cpp/pcsx2/x86/microVU_Compile.inl
index 65cf31b..2d3a3f8 100644
--- a/app/src/main/cpp/pcsx2/x86/microVU_Compile.inl
+++ b/app/src/main/cpp/pcsx2/x86/microVU_Compile.inl
@@ -515,7 +515,7 @@ void mVUtestCycles(microVU& mVU, microFlagCycles& mFC)
     armAsm->B(&skip, a64::Condition::pl);
 
 //	xLoadFarAddr(rax, &mVUpBlock->pState);
-    armMoveAddressToReg(RAX, &mVUpBlock->pState);
+    armAsm->Ldr(RAX, PTR_MBLOCK(pState));
 //	xCALL((void*)mVU.copyPLState);
     armEmitCall(mVU.copyPLState);
 
diff --git a/app/src/main/cpp/pcsx2/x86/microVU_Misc.inl b/app/src/main/cpp/pcsx2/x86/microVU_Misc.inl
index b821da0..64130d3 100644
--- a/app/src/main/cpp/pcsx2/x86/microVU_Misc.inl
+++ b/app/src/main/cpp/pcsx2/x86/microVU_Misc.inl
@@ -445,17 +445,17 @@ __fi std::optional<a64::MemOperand> mVUoptimizeConstantAddr(mV, u32 srcreg, s32
 // Micro VU - Custom SSE Instructions
 //------------------------------------------------------------------
 
-struct SSEMasks
-{
-	u32 MIN_MAX_1[4], MIN_MAX_2[4], ADD_SS[4];
-};
+//struct SSEMasks
+//{
+//	u32 MIN_MAX_1[4], MIN_MAX_2[4], ADD_SS[4];
+//};
 
-alignas(16) static const SSEMasks sseMasks =
-{
-	{0xffffffff, 0x80000000, 0xffffffff, 0x80000000},
-	{0x00000000, 0x40000000, 0x00000000, 0x40000000},
-	{0x80000000, 0xffffffff, 0xffffffff, 0xffffffff},
-};
+//alignas(16) static const SSEMasks sseMasks =
+//{
+//	{0xffffffff, 0x80000000, 0xffffffff, 0x80000000},
+//	{0x00000000, 0x40000000, 0x00000000, 0x40000000},
+//	{0x80000000, 0xffffffff, 0xffffffff, 0xffffffff},
+//};
 
 
 // Warning: Modifies t1 and t2
@@ -470,15 +470,15 @@ void MIN_MAX_PS(microVU& mVU, const xmm& to, const xmm& from, const xmm& t1in, c
 //		xPSHUF.D(t1, to, 0xfa); 1234 => 3344
         armPSHUFD(t1, to, 0xfa);
 //		xPAND   (t1, ptr128[sseMasks.MIN_MAX_1]);
-        armAsm->And(t1.V16B(), t1.V16B(), armLoadPtrV(sseMasks.MIN_MAX_1).V16B());
+        armAsm->And(t1.V16B(), t1.V16B(), armLoadPtrV(PTR_CPU(mVUss4.sseMasks.MIN_MAX_1)).V16B());
 //		xPOR    (t1, ptr128[sseMasks.MIN_MAX_2]);
-        armAsm->Orr(t1.V16B(), t1.V16B(), armLoadPtrV(sseMasks.MIN_MAX_2).V16B());
+        armAsm->Orr(t1.V16B(), t1.V16B(), armLoadPtrV(PTR_CPU(mVUss4.sseMasks.MIN_MAX_2)).V16B());
 //		xPSHUF.D(t2, from, 0xfa); 1234 => 3344
         armPSHUFD(t2, from, 0xfa);
 //		xPAND   (t2, ptr128[sseMasks.MIN_MAX_1]);
-        armAsm->And(t2.V16B(), t2.V16B(), armLoadPtrV(sseMasks.MIN_MAX_1).V16B());
+        armAsm->And(t2.V16B(), t2.V16B(), armLoadPtrV(PTR_CPU(mVUss4.sseMasks.MIN_MAX_1)).V16B());
 //		xPOR    (t2, ptr128[sseMasks.MIN_MAX_2]);
-        armAsm->Orr(t2.V16B(), t2.V16B(), armLoadPtrV(sseMasks.MIN_MAX_2).V16B());
+        armAsm->Orr(t2.V16B(), t2.V16B(), armLoadPtrV(PTR_CPU(mVUss4.sseMasks.MIN_MAX_2)).V16B());
 //		if (min) xMIN.PD(t1, t2);
         if (min) armAsm->Fminnm(t1.V2D(), t1.V2D(), t2.V2D());
 //		else     xMAX.PD(t1, t2);
@@ -488,15 +488,15 @@ void MIN_MAX_PS(microVU& mVU, const xmm& to, const xmm& from, const xmm& t1in, c
 //		xPSHUF.D(t2, from, 0x50); 1234 => 1122
         armPSHUFD(t2, from, 0x50);
 //		xPAND   (t2, ptr128[sseMasks.MIN_MAX_1]);
-        armAsm->And(t2.V16B(), t2.V16B(), armLoadPtrV(sseMasks.MIN_MAX_1).V16B());
+        armAsm->And(t2.V16B(), t2.V16B(), armLoadPtrV(PTR_CPU(mVUss4.sseMasks.MIN_MAX_1)).V16B());
 //		xPOR    (t2, ptr128[sseMasks.MIN_MAX_2]);
-        armAsm->Orr(t2.V16B(), t2.V16B(), armLoadPtrV(sseMasks.MIN_MAX_2).V16B());
+        armAsm->Orr(t2.V16B(), t2.V16B(), armLoadPtrV(PTR_CPU(mVUss4.sseMasks.MIN_MAX_2)).V16B());
 //		xPSHUF.D(to, to, 0x50); 1234 => 1122
         armPSHUFD(to, to, 0x50);
 //		xPAND   (to, ptr128[sseMasks.MIN_MAX_1]);
-        armAsm->And(to.V16B(), to.V16B(), armLoadPtrV(sseMasks.MIN_MAX_1).V16B());
+        armAsm->And(to.V16B(), to.V16B(), armLoadPtrV(PTR_CPU(mVUss4.sseMasks.MIN_MAX_1)).V16B());
 //		xPOR    (to, ptr128[sseMasks.MIN_MAX_2]);
-        armAsm->Orr(to.V16B(), to.V16B(), armLoadPtrV(sseMasks.MIN_MAX_2).V16B());
+        armAsm->Orr(to.V16B(), to.V16B(), armLoadPtrV(PTR_CPU(mVUss4.sseMasks.MIN_MAX_2)).V16B());
 //		if (min) xMIN.PD(to, t2);
 //		else     xMAX.PD(to, t2);
         if (min) armAsm->Fminnm(to.V2D(), to.V2D(), t2.V2D());
@@ -551,9 +551,9 @@ void MIN_MAX_SS(mV, const xmm& to, const xmm& from, const xmm& t1in, bool min)
 //	xSHUF.PS(to, from, 0);
     armSHUFPS(to, from, 0);
 //	xPAND   (to, ptr128[sseMasks.MIN_MAX_1]);
-    armAsm->And(to.V16B(), to.V16B(), armLoadPtrV(sseMasks.MIN_MAX_1).V16B());
+    armAsm->And(to.V16B(), to.V16B(), armLoadPtrV(PTR_CPU(mVUss4.sseMasks.MIN_MAX_1)).V16B());
 //	xPOR    (to, ptr128[sseMasks.MIN_MAX_2]);
-    armAsm->Orr(to.V16B(), to.V16B(), armLoadPtrV(sseMasks.MIN_MAX_2).V16B());
+    armAsm->Orr(to.V16B(), to.V16B(), armLoadPtrV(PTR_CPU(mVUss4.sseMasks.MIN_MAX_2)).V16B());
 //	xPSHUF.D(t1, to, 0xee);
     armAsm->Dup(t1.V2D(), to.V2D(), 1); //v3v2v3v2
 //	if (min) xMIN.PD(to, t1);
@@ -602,7 +602,7 @@ void ADD_SS_Single_Guard_Bit(microVU& mVU, const xmm& to, const xmm& from, const
 
     // case_pos_big:
 //	xPAND(to, ptr128[sseMasks.ADD_SS]);
-    armAsm->And(to.V16B(), to.V16B(), armLoadPtrV(sseMasks.ADD_SS).V16B());
+    armAsm->And(to.V16B(), to.V16B(), armLoadPtrV(PTR_CPU(mVUss4.sseMasks.ADD_SS)).V16B());
 //	xForwardJump8 case_end2;
     a64::Label case_end2;
     armAsm->B(&case_end2);
@@ -633,7 +633,7 @@ void ADD_SS_Single_Guard_Bit(microVU& mVU, const xmm& to, const xmm& from, const
 
     // case_neg_big:
 //	xPAND(from, ptr128[sseMasks.ADD_SS]);
-    armAsm->And(from.V16B(), from.V16B(), armLoadPtrV(sseMasks.ADD_SS).V16B());
+    armAsm->And(from.V16B(), from.V16B(), armLoadPtrV(PTR_CPU(mVUss4.sseMasks.ADD_SS)).V16B());
 //	xForwardJump8 case_end4;
     a64::Label case_end4;
     armAsm->B(&case_end4);
@@ -698,7 +698,7 @@ void ADD_SS_TriAceHack(microVU& mVU, const xmm& to, const xmm& from)
 
     // case_pos_big:
 //	xPAND(to, ptr128[sseMasks.ADD_SS]);
-    armAsm->And(to.V16B(), to.V16B(), armLoadPtrV(sseMasks.ADD_SS).V16B());
+    armAsm->And(to.V16B(), to.V16B(), armLoadPtrV(PTR_CPU(mVUss4.sseMasks.ADD_SS)).V16B());
 //	xForwardJump8 case_end2;
     a64::Label case_end2;
     armAsm->B(&case_end2);
@@ -706,7 +706,7 @@ void ADD_SS_TriAceHack(microVU& mVU, const xmm& to, const xmm& from)
 //	case_neg_big.SetTarget();
     armBind(&case_neg_big);
 //	xPAND(from, ptr128[sseMasks.ADD_SS]);
-    armAsm->And(from.V16B(), from.V16B(), armLoadPtrV(sseMasks.ADD_SS).V16B());
+    armAsm->And(from.V16B(), from.V16B(), armLoadPtrV(PTR_CPU(mVUss4.sseMasks.ADD_SS)).V16B());
 
 //	case_end1.SetTarget();
     armBind(&case_end1);