Diddy-Kong-Racing/tools/python/generate_ld.py

import re
import os
import sys

from file_util import FileUtil
from generate_assets import GenerateAssets

VERSION = sys.argv[1]

if VERSION != 'us_1.0':
    print("generate_ld currently does not support " + sys.argv[1])
    sys.exit(0)

ROOT_DIR = '.'
LD_NAME = ROOT_DIR + '/dkr.ld'
ASM_DIR = ROOT_DIR + '/asm'
SRC_DIR = ROOT_DIR + '/src'
LIB_ASM_DIR = ROOT_DIR + '/lib/asm'
LIB_SRC_DIR = ROOT_DIR + '/lib/src'
BUILD_DIR = 'build/' + VERSION

class GenerateLD:
    def __init__(self, file):
        print('Generating linker file...')
        self.assets = GenerateAssets(ROOT_DIR, VERSION)
        self.files = self.get_code_files()
        self.indentLevel = 0
        self.file = file
        self.gen_comment('linker script generated by generate_ld.py')
        self.gen_newline()
        self.gen_line('OUTPUT_ARCH (mips)')
        self.gen_newline()
        self.gen_sections()
        print('New linker file created!')
        
    def gen_sections(self):
        self.gen_line('SECTIONS')
        self.gen_open_block()
        self.gen_line('romPos = 0x0;')
        self.gen_boot_section()
        self.gen_main_section()
        self.gen_ucode_text_section()
        self.gen_data_section()
        self.gen_ucode_data_section()
        self.gen_assets_section()
        self.gen_discard()
        self.gen_close_block()
    
    def gen_boot_section(self):
        self.gen_line('.boot 0 : AT(romPos)')
        self.gen_open_block()
        self.gen_line(BUILD_DIR + '/asm/boot/rom_header.o(.text);')
        self.gen_line(BUILD_DIR + '/asm/boot/rom_boot.o(.text);')
        self.gen_close_block()
        self.gen_line('romPos += SIZEOF(.boot);')
        self.gen_newline()
    
    def gen_main_section(self):
        self.gen_line('.main 0x80000400 : AT(romPos) SUBALIGN(16)')
        self.gen_open_block()
        for file in self.files:
            self.gen_line(file[0] + '(.text);')
        self.gen_close_block()
        self.gen_line('romPos += SIZEOF(.main);')
        self.gen_newline()
        
    def gen_ucode_text_section(self):
        self.gen_line('.ucodeText 0 : AT(romPos)')
        self.gen_open_block()
        self.gen_line(BUILD_DIR + '/asm/assets/ucode_text.o(.text);')
        self.gen_close_block()
        self.gen_line('romPos += SIZEOF(.ucodeText);')
        self.gen_newline()
        
    def gen_data_section(self):
        self.gen_line('.main_data 0x80000400 : AT(romPos) SUBALIGN(16)')
        self.gen_open_block()
        for file in self.files:
            self.gen_line(file[0] + '(.data);')
        self.gen_line(BUILD_DIR + '/data/dkr.data.o(.data);')
        self.gen_close_block()
        self.gen_line('romPos += SIZEOF(.main_data);')
        self.gen_newline()
        
    def gen_ucode_data_section(self):
        self.gen_line('.ucodeData 0 : AT(romPos)')
        self.gen_open_block()
        self.gen_line(BUILD_DIR + '/asm/assets/ucode_data.o(.text);')
        self.gen_close_block()
        self.gen_line('romPos += SIZEOF(.ucodeData);')
        self.gen_newline()
        
    def gen_assets_section(self):
        self.gen_line('__ASSETS_LUT_START = romPos;');
        self.gen_line('__ASSETS_LUT_END = __ASSETS_LUT_START + ' + hex((((self.assets.numAssets + 2) * 4) + 15) & 0xFFFFFFF0) + ';');
        self.gen_newline()
        self.gen_line('.assets 0 : AT(romPos)')
        self.gen_open_block()
        self.gen_line(BUILD_DIR + '/asm/assets/assets.o(.text);')
        self.gen_close_block()
        self.gen_line('romPos += SIZEOF(.assets);')
        self.gen_newline()
        
    def gen_discard(self):
        self.gen_comment('Discard everything not specifically mentioned above.')
        self.gen_line('/DISCARD/ :')
        self.gen_open_block()
        self.gen_line('*(*);')
        self.gen_close_block()
    
    def increase_indent(self):
        self.indentLevel += 1
    
    def decrease_indent(self):
        self.indentLevel -= 1
        
    def gen_open_block(self):
        self.gen_line('{')
        self.increase_indent()
        
    def gen_close_block(self):
        self.decrease_indent()
        self.gen_line('}')
    
    def gen_line(self, text):
        spaces = 4 * self.indentLevel
        while spaces > 0:
            self.file.write(' ')
            spaces -= 1
        self.file.write(text)
        self.gen_newline()
        
    def gen_comment(self, text):
        spaces = 4 * self.indentLevel
        while spaces > 0:
            self.file.write(' ')
            spaces -= 1
        self.file.write('/* ' + text + ' */')
        self.gen_newline()
        
    def gen_newline(self):
        self.file.write('\n')
        
    def append_files(self, files, extensions, directory, outputDir):
        filenames = FileUtil.get_filenames_from_directory(directory, extensions)
        regex = r'[\/][*]+\s*RAM_POS:\s*0x([0-9a-fA-F]+)\s*[*]+[\/]'
        for filename in filenames:
            with open(directory + '/' + filename, 'r') as inFile:
                notDone = True
                line = inFile.readline()
                while line:
                    matches = re.match(regex, line)
                    if matches is None:
                        line = inFile.readline()
                        continue
                    matchedGroups = matches.groups()
                    files.append((outputDir + filename[:-2] + '.o', '', matchedGroups[0], 0))
                    break

    def get_code_files(self):
        files = []
        self.append_files(files, ('.s',), ASM_DIR, BUILD_DIR + '/asm/')
        self.append_files(files, ('.c',), SRC_DIR, BUILD_DIR + '/src/')
        self.append_files(files, ('.s',), LIB_ASM_DIR, BUILD_DIR + '/lib/asm/')
        self.append_files(files, ('.c',), LIB_SRC_DIR, BUILD_DIR + '/lib/src/')
        files.sort(key = lambda x: (x[2], x[3])) # Sort tuples by RAM address and prioritize src files first.
        return files

with open(LD_NAME, 'w') as ldFile:
    GenerateLD(ldFile)