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move more of d_save / d_com_inf_game (#141)

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* some d_save matches / fixes

* more d_save cleanup

* fopAc_ac_c changes

* move a bunch of d_save / d_com_inf_game stuff

* format + remove asm

* move bit labels to correct header

* format

* move d_item

* fix check_itemno doc

* move

* fixes

* getLayerNo_common_common almost matching

just regalloc issues

* small fixes

* few more matches

* fix
This commit is contained in:
TakaRikka
2021-08-23 22:47:18 +02:00
committed by GitHub
parent f6df420a61
commit e14b04c54a
422 changed files with 4869 additions and 14588 deletions
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asm/d/event/d_event/func_80041488.s
-63
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@@ -1,63 +0,0 @@
lbl_80041488:
/* 80041488 94 21 FF F0 */ stwu r1, -0x10(r1)
/* 8004148C 7C 08 02 A6 */ mflr r0
/* 80041490 90 01 00 14 */ stw r0, 0x14(r1)
/* 80041494 93 E1 00 0C */ stw r31, 0xc(r1)
/* 80041498 3C 60 80 40 */ lis r3, g_dComIfG_gameInfo@ha /* 0x804061C0@ha */
/* 8004149C 38 63 61 C0 */ addi r3, r3, g_dComIfG_gameInfo@l /* 0x804061C0@l */
/* 800414A0 3B E3 0D D8 */ addi r31, r3, 0xdd8
/* 800414A4 7F E3 FB 78 */ mr r3, r31
/* 800414A8 3C 80 80 38 */ lis r4, tempBitLabels__20dSv_event_tmp_flag_c@ha /* 0x803790C0@ha */
/* 800414AC 38 84 90 C0 */ addi r4, r4, tempBitLabels__20dSv_event_tmp_flag_c@l /* 0x803790C0@l */
/* 800414B0 A0 84 00 16 */ lhz r4, 0x16(r4)
/* 800414B4 4B FF 34 F1 */ bl offEventBit__11dSv_event_cFUs
/* 800414B8 7F E3 FB 78 */ mr r3, r31
/* 800414BC 3C 80 80 38 */ lis r4, tempBitLabels__20dSv_event_tmp_flag_c@ha /* 0x803790C0@ha */
/* 800414C0 38 84 90 C0 */ addi r4, r4, tempBitLabels__20dSv_event_tmp_flag_c@l /* 0x803790C0@l */
/* 800414C4 A0 84 00 18 */ lhz r4, 0x18(r4)
/* 800414C8 4B FF 34 DD */ bl offEventBit__11dSv_event_cFUs
/* 800414CC 7F E3 FB 78 */ mr r3, r31
/* 800414D0 3C 80 80 38 */ lis r4, tempBitLabels__20dSv_event_tmp_flag_c@ha /* 0x803790C0@ha */
/* 800414D4 38 84 90 C0 */ addi r4, r4, tempBitLabels__20dSv_event_tmp_flag_c@l /* 0x803790C0@l */
/* 800414D8 A0 84 00 1A */ lhz r4, 0x1a(r4)
/* 800414DC 4B FF 34 C9 */ bl offEventBit__11dSv_event_cFUs
/* 800414E0 7F E3 FB 78 */ mr r3, r31
/* 800414E4 3C 80 80 38 */ lis r4, tempBitLabels__20dSv_event_tmp_flag_c@ha /* 0x803790C0@ha */
/* 800414E8 38 84 90 C0 */ addi r4, r4, tempBitLabels__20dSv_event_tmp_flag_c@l /* 0x803790C0@l */
/* 800414EC A0 84 00 1C */ lhz r4, 0x1c(r4)
/* 800414F0 4B FF 34 B5 */ bl offEventBit__11dSv_event_cFUs
/* 800414F4 7F E3 FB 78 */ mr r3, r31
/* 800414F8 3C 80 80 38 */ lis r4, tempBitLabels__20dSv_event_tmp_flag_c@ha /* 0x803790C0@ha */
/* 800414FC 38 84 90 C0 */ addi r4, r4, tempBitLabels__20dSv_event_tmp_flag_c@l /* 0x803790C0@l */
/* 80041500 A0 84 00 1E */ lhz r4, 0x1e(r4)
/* 80041504 4B FF 34 A1 */ bl offEventBit__11dSv_event_cFUs
/* 80041508 7F E3 FB 78 */ mr r3, r31
/* 8004150C 3C 80 80 38 */ lis r4, tempBitLabels__20dSv_event_tmp_flag_c@ha /* 0x803790C0@ha */
/* 80041510 38 84 90 C0 */ addi r4, r4, tempBitLabels__20dSv_event_tmp_flag_c@l /* 0x803790C0@l */
/* 80041514 A0 84 00 66 */ lhz r4, 0x66(r4)
/* 80041518 4B FF 34 8D */ bl offEventBit__11dSv_event_cFUs
/* 8004151C 7F E3 FB 78 */ mr r3, r31
/* 80041520 3C 80 80 38 */ lis r4, tempBitLabels__20dSv_event_tmp_flag_c@ha /* 0x803790C0@ha */
/* 80041524 38 84 90 C0 */ addi r4, r4, tempBitLabels__20dSv_event_tmp_flag_c@l /* 0x803790C0@l */
/* 80041528 A0 84 00 68 */ lhz r4, 0x68(r4)
/* 8004152C 4B FF 34 79 */ bl offEventBit__11dSv_event_cFUs
/* 80041530 7F E3 FB 78 */ mr r3, r31
/* 80041534 3C 80 80 38 */ lis r4, tempBitLabels__20dSv_event_tmp_flag_c@ha /* 0x803790C0@ha */
/* 80041538 38 84 90 C0 */ addi r4, r4, tempBitLabels__20dSv_event_tmp_flag_c@l /* 0x803790C0@l */
/* 8004153C A0 84 00 6A */ lhz r4, 0x6a(r4)
/* 80041540 4B FF 34 65 */ bl offEventBit__11dSv_event_cFUs
/* 80041544 7F E3 FB 78 */ mr r3, r31
/* 80041548 3C 80 80 38 */ lis r4, tempBitLabels__20dSv_event_tmp_flag_c@ha /* 0x803790C0@ha */
/* 8004154C 38 84 90 C0 */ addi r4, r4, tempBitLabels__20dSv_event_tmp_flag_c@l /* 0x803790C0@l */
/* 80041550 A0 84 00 6C */ lhz r4, 0x6c(r4)
/* 80041554 4B FF 34 51 */ bl offEventBit__11dSv_event_cFUs
/* 80041558 7F E3 FB 78 */ mr r3, r31
/* 8004155C 3C 80 80 38 */ lis r4, tempBitLabels__20dSv_event_tmp_flag_c@ha /* 0x803790C0@ha */
/* 80041560 38 84 90 C0 */ addi r4, r4, tempBitLabels__20dSv_event_tmp_flag_c@l /* 0x803790C0@l */
/* 80041564 A0 84 00 6E */ lhz r4, 0x6e(r4)
/* 80041568 4B FF 34 3D */ bl offEventBit__11dSv_event_cFUs
/* 8004156C 83 E1 00 0C */ lwz r31, 0xc(r1)
/* 80041570 80 01 00 14 */ lwz r0, 0x14(r1)
/* 80041574 7C 08 03 A6 */ mtlr r0
/* 80041578 38 21 00 10 */ addi r1, r1, 0x10
/* 8004157C 4E 80 00 20 */ blr
asm/d/event/d_event/orderOld__14dEvt_control_cFUsUsUsUsPvPvPCv.s
-37
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@@ -1,37 +0,0 @@
lbl_800415D8:
/* 800415D8 94 21 FF D0 */ stwu r1, -0x30(r1)
/* 800415DC 7C 08 02 A6 */ mflr r0
/* 800415E0 90 01 00 34 */ stw r0, 0x34(r1)
/* 800415E4 39 61 00 30 */ addi r11, r1, 0x30
/* 800415E8 48 32 0B E5 */ bl _savegpr_25
/* 800415EC 7C 79 1B 78 */ mr r25, r3
/* 800415F0 7C 9A 23 78 */ mr r26, r4
/* 800415F4 7C BB 2B 78 */ mr r27, r5
/* 800415F8 7C DC 33 78 */ mr r28, r6
/* 800415FC 7C FD 3B 78 */ mr r29, r7
/* 80041600 7D 1E 43 78 */ mr r30, r8
/* 80041604 7D 3F 4B 78 */ mr r31, r9
/* 80041608 3C 60 80 40 */ lis r3, g_dComIfG_gameInfo@ha /* 0x804061C0@ha */
/* 8004160C 38 63 61 C0 */ addi r3, r3, g_dComIfG_gameInfo@l /* 0x804061C0@l */
/* 80041610 38 63 4F F8 */ addi r3, r3, 0x4ff8
/* 80041614 7D 44 53 78 */ mr r4, r10
/* 80041618 38 A0 00 FF */ li r5, 0xff
/* 8004161C 38 C0 FF FF */ li r6, -1
/* 80041620 48 00 5E F5 */ bl getEventIdx__16dEvent_manager_cFPCcUcl
/* 80041624 7C 6A 07 34 */ extsh r10, r3
/* 80041628 38 00 00 FF */ li r0, 0xff
/* 8004162C 90 01 00 08 */ stw r0, 8(r1)
/* 80041630 7F 23 CB 78 */ mr r3, r25
/* 80041634 7F 44 D3 78 */ mr r4, r26
/* 80041638 7F 65 DB 78 */ mr r5, r27
/* 8004163C 7F 86 E3 78 */ mr r6, r28
/* 80041640 7F A7 EB 78 */ mr r7, r29
/* 80041644 7F C8 F3 78 */ mr r8, r30
/* 80041648 7F E9 FB 78 */ mr r9, r31
/* 8004164C 48 00 00 1D */ bl order__14dEvt_control_cFUsUsUsUsPvPvsUc
/* 80041650 39 61 00 30 */ addi r11, r1, 0x30
/* 80041654 48 32 0B C5 */ bl _restgpr_25
/* 80041658 80 01 00 34 */ lwz r0, 0x34(r1)
/* 8004165C 7C 08 03 A6 */ mtlr r0
/* 80041660 38 21 00 30 */ addi r1, r1, 0x30
/* 80041664 4E 80 00 20 */ blr