Files
tp/libs/SSystem/SComponent/c_m3d_g_pla.cpp
T

130 lines
3.9 KiB
C++
Raw Normal View History

2021-03-29 00:10:25 +02:00
//
2021-03-28 22:49:05 +02:00
// Generated By: dol2asm
// Translation Unit: c_m3d_g_pla
2021-03-29 00:10:25 +02:00
//
2021-01-07 02:04:53 +01:00
2021-03-29 00:10:25 +02:00
#include "SSystem/SComponent/c_m3d_g_pla.h"
2021-03-28 22:49:05 +02:00
#include "dol2asm.h"
#include "dolphin/types.h"
2021-01-31 15:33:34 -05:00
2021-03-29 00:10:25 +02:00
//
2021-03-28 22:49:05 +02:00
// Types:
2021-03-29 00:10:25 +02:00
//
2021-02-20 23:11:44 -05:00
2021-03-29 00:10:25 +02:00
struct cXyz {};
2021-01-07 02:04:53 +01:00
2021-03-29 00:10:25 +02:00
struct Vec {};
2021-03-28 22:49:05 +02:00
struct cM3dGPla {
2021-03-29 00:10:25 +02:00
/* 8026F3DC */ cM3dGPla(cXyz const*, f32);
/* 8026F408 */ void crossInfLin(cXyz const&, cXyz const&, cXyz&) const;
/* 8026F4C4 */ void SetupNP0(Vec const&, Vec const&);
/* 8026F52C */ void SetupNP(Vec const&, Vec const&);
/* 8026F57C */ void getCrossY(cXyz const&, f32*) const;
/* 8026F5D4 */ void getCrossYLessD(Vec const&, f32*) const;
/* 8026F624 */ void Set(cM3dGPla const*);
2021-03-28 22:49:05 +02:00
};
2021-03-29 00:10:25 +02:00
//
2021-03-28 22:49:05 +02:00
// Forward References:
2021-03-29 00:10:25 +02:00
//
2021-03-28 22:49:05 +02:00
extern "C" void __ct__8cM3dGPlaFPC4cXyzf();
extern "C" void crossInfLin__8cM3dGPlaCFRC4cXyzRC4cXyzR4cXyz();
extern "C" void SetupNP0__8cM3dGPlaFRC3VecRC3Vec();
extern "C" void SetupNP__8cM3dGPlaFRC3VecRC3Vec();
extern "C" void getCrossY__8cM3dGPlaCFRC4cXyzPf();
extern "C" void getCrossYLessD__8cM3dGPlaCFRC3VecPf();
extern "C" void Set__8cM3dGPlaFPC8cM3dGPla();
2021-03-29 00:10:25 +02:00
//
2021-03-28 22:49:05 +02:00
// External References:
2021-03-29 00:10:25 +02:00
//
2021-03-28 22:49:05 +02:00
void cM3d_InDivPos2(Vec const*, Vec const*, f32, Vec*);
extern "C" extern void* __vt__8cM3dGPla[3];
extern "C" extern f32 G_CM3D_F_ABS_MIN[1 + 1 /* padding */];
extern "C" void cM3d_InDivPos2__FPC3VecPC3VecfP3Vec();
extern "C" void PSVECNormalize();
extern "C" void PSVECDotProduct();
extern "C" void _savegpr_28();
extern "C" void _restgpr_28();
extern "C" extern void* __vt__8cM3dGPla[3];
extern "C" extern f32 G_CM3D_F_ABS_MIN[1 + 1 /* padding */];
2021-03-29 00:10:25 +02:00
//
2021-03-28 22:49:05 +02:00
// Declarations:
2021-03-29 00:10:25 +02:00
//
2021-03-28 22:49:05 +02:00
2021-03-29 00:10:25 +02:00
/* 8026F3DC-8026F408 002C+00 s=0 e=3 z=0 None .text __ct__8cM3dGPlaFPC4cXyzf */
2021-03-28 22:49:05 +02:00
#pragma push
#pragma optimization_level 0
#pragma optimizewithasm off
asm cM3dGPla::cM3dGPla(cXyz const* param_0, f32 param_1) {
2021-03-29 00:10:25 +02:00
nofralloc
2021-03-28 22:49:05 +02:00
#include "asm/SSystem/SComponent/c_m3d_g_pla/__ct__8cM3dGPlaFPC4cXyzf.s"
2021-01-07 02:04:53 +01:00
}
2021-03-28 22:49:05 +02:00
#pragma pop
2021-01-07 02:04:53 +01:00
2021-03-29 00:10:25 +02:00
/* 8026F408-8026F4C4 00BC+00 s=0 e=3 z=0 None .text crossInfLin__8cM3dGPlaCFRC4cXyzRC4cXyzR4cXyz
*/
2021-03-28 22:49:05 +02:00
#pragma push
#pragma optimization_level 0
#pragma optimizewithasm off
asm void cM3dGPla::crossInfLin(cXyz const& param_0, cXyz const& param_1, cXyz& param_2) const {
2021-03-29 00:10:25 +02:00
nofralloc
2021-03-28 22:49:05 +02:00
#include "asm/SSystem/SComponent/c_m3d_g_pla/crossInfLin__8cM3dGPlaCFRC4cXyzRC4cXyzR4cXyz.s"
2021-01-07 02:04:53 +01:00
}
2021-03-28 22:49:05 +02:00
#pragma pop
2021-01-07 02:04:53 +01:00
2021-03-29 00:10:25 +02:00
/* 8026F4C4-8026F52C 0068+00 s=0 e=1 z=0 None .text SetupNP0__8cM3dGPlaFRC3VecRC3Vec */
2021-03-28 22:49:05 +02:00
#pragma push
#pragma optimization_level 0
#pragma optimizewithasm off
asm void cM3dGPla::SetupNP0(Vec const& param_0, Vec const& param_1) {
2021-03-29 00:10:25 +02:00
nofralloc
2021-03-28 22:49:05 +02:00
#include "asm/SSystem/SComponent/c_m3d_g_pla/SetupNP0__8cM3dGPlaFRC3VecRC3Vec.s"
2021-01-07 02:04:53 +01:00
}
2021-03-28 22:49:05 +02:00
#pragma pop
2021-01-07 02:04:53 +01:00
2021-03-29 00:10:25 +02:00
/* 8026F52C-8026F57C 0050+00 s=0 e=2 z=0 None .text SetupNP__8cM3dGPlaFRC3VecRC3Vec */
2021-03-28 22:49:05 +02:00
#pragma push
#pragma optimization_level 0
#pragma optimizewithasm off
asm void cM3dGPla::SetupNP(Vec const& param_0, Vec const& param_1) {
2021-03-29 00:10:25 +02:00
nofralloc
2021-03-28 22:49:05 +02:00
#include "asm/SSystem/SComponent/c_m3d_g_pla/SetupNP__8cM3dGPlaFRC3VecRC3Vec.s"
2021-01-07 02:04:53 +01:00
}
2021-03-28 22:49:05 +02:00
#pragma pop
2021-03-29 00:10:25 +02:00
/* 8026F57C-8026F5D4 0058+00 s=0 e=2 z=0 None .text getCrossY__8cM3dGPlaCFRC4cXyzPf */
2021-03-28 22:49:05 +02:00
#pragma push
#pragma optimization_level 0
#pragma optimizewithasm off
asm void cM3dGPla::getCrossY(cXyz const& param_0, f32* param_1) const {
2021-03-29 00:10:25 +02:00
nofralloc
2021-03-28 22:49:05 +02:00
#include "asm/SSystem/SComponent/c_m3d_g_pla/getCrossY__8cM3dGPlaCFRC4cXyzPf.s"
}
#pragma pop
2021-03-29 00:10:25 +02:00
/* 8026F5D4-8026F624 0050+00 s=0 e=1 z=0 None .text getCrossYLessD__8cM3dGPlaCFRC3VecPf */
2021-03-28 22:49:05 +02:00
#pragma push
#pragma optimization_level 0
#pragma optimizewithasm off
asm void cM3dGPla::getCrossYLessD(Vec const& param_0, f32* param_1) const {
2021-03-29 00:10:25 +02:00
nofralloc
2021-03-28 22:49:05 +02:00
#include "asm/SSystem/SComponent/c_m3d_g_pla/getCrossYLessD__8cM3dGPlaCFRC3VecPf.s"
}
#pragma pop
2021-03-29 00:10:25 +02:00
/* 8026F624-8026F648 0024+00 s=0 e=1 z=0 None .text Set__8cM3dGPlaFPC8cM3dGPla */
2021-03-28 22:49:05 +02:00
#pragma push
#pragma optimization_level 0
#pragma optimizewithasm off
asm void cM3dGPla::Set(cM3dGPla const* param_0) {
2021-03-29 00:10:25 +02:00
nofralloc
2021-03-28 22:49:05 +02:00
#include "asm/SSystem/SComponent/c_m3d_g_pla/Set__8cM3dGPlaFPC8cM3dGPla.s"
}
#pragma pop