/* Linker configuration for building a static (.dol) module */ MEMORY { text : origin = 0x80003100 } SECTIONS { GROUP : { /* RAM addr DOL file pos Size */ .init ALIGN(0x20) : {} /* 0x80003100 0x000100 0x0023A8 */ _extab ALIGN(0x20) : {} /* 0x800054C0 0x10B780 0x0006A8 */ _extabindex ALIGN(0x20) : {} /* 0x80005B80 0x10BE40 0x000A1C */ .text ALIGN(0x20) : {} /* 0x800065A0 0x0024C0 0x1092BC */ .ctors ALIGN(0x20) : {} /* 0x8010F860 0x10C860 0x00000C */ .dtors ALIGN(0x20) : {} /* 0x8010F880 0x10C880 0x000010 */ .rodata ALIGN(0x20) : {} /* 0x8010F8A0 0x10C8A0 0x062ADC */ .data ALIGN(0x20) : {} /* 0x80172380 0x16F380 0x07B591 */ .bss ALIGN(0x20) : {} /* 0x801ED920 n/a 0x1028C0 */ .sdata ALIGN(0x20) : {} /* 0x802F01E0 0x1EA920 0x0018F9 */ .sbss ALIGN(0x20) : {} /* 0x802F1AE0 n/a 0x000D15 */ .sdata2 ALIGN(0x20) : {} /* 0x802F2800 0x1EC220 0x004480 */ .sbss2 ALIGN(0x20) : {} /* unused */ /* GCC generated sections */ .rodata.str1.4 ALIGN(0x20) : {} .rodata.cst4 ALIGN(0x20) : {} .rodata.cst8 ALIGN(0x20) : {} .stack ALIGN(0x100) : {} } > text /* stack immediately follows last section */ _stack_end = _f_stack; _stack_addr = (_stack_end + 0x10000 + 0x7) & ~0x7; /* debug immediately follows normal stack */ _db_stack_end = _stack_addr; _db_stack_addr = _db_stack_end + 0x2000; /* arena follows debug stack */ __ArenaLo = (_db_stack_addr + 0x1F) & ~ 0x1F; __ArenaHi = 0x81700000; } FORCEACTIVE { lbl_802C4960 lbl_802F1FEC unused802B4B20 lbl_80285A68 lbl_80285A80 lbl_802F1FB4 lbl_802F1FAC lbl_802F1FA8 } lbl_80292C00_alias = lbl_80292C00; /* For GCC compatibility */ __udivdi3 = __div2u; lbl_801B9BB0 = 0x801B9BB0; lbl_802F4234 = 0x802F4234; lbl_802F4238 = 0x802F4238; lbl_802F4240 = 0x802F4240; lbl_802F4244 = 0x802F4244; lbl_802F424C = 0x802F424C; lbl_802F4254 = 0x802F4254; lbl_802F4258 = 0x802F4258; lbl_802F425C = 0x802F425C; lbl_802F4270 = 0x802F4270; lbl_802F428C = 0x802F428C; lbl_802F42A0 = 0x802F42A0; lbl_802F42A8 = 0x802F42A8; lbl_802F42AC = 0x802F42AC; lbl_802F42B0 = 0x802F42B0; lbl_802F42B4 = 0x802F42B4; lbl_802F42B8 = 0x802F42B8;