mirror of
https://github.com/encounter/oot-gc.git
synced 2026-03-30 11:33:44 -07:00
Yanis
314 lines
11 KiB
SQL
314 lines
11 KiB
SQL
/*
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Code sections:
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.init 80003100 - 80005598 : 002498
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.text 800055A0 - 800D2F8C : 0CD9EC
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Data sections:
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.ctors 800D2FA0 - 800D2FA8 : 000008
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.dtors 800D2FC0 - 800D2FC8 : 000008
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.rodata 800D2FE0 - 800D3710 : 000730
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.data 800D3720 - 800F3ED8 : 0207B8
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.sdata 80134CE0 - 80135579 : 000899
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.sdata2 80135D00 - 80136420 : 000720
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BSS section:
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.bss 800F3EE0 - 80134CD8 : 040DF8
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.sbss 80135580 - 80135CFD : 00077D
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.sbss2 80136420 - 80136420 : 000000
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Entry Point: 0x80003154
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*/
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# glabel
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.macro glabel label
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.global \label
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\label:
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.endm
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# PowerPC Register Constants
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.set r0, 0
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.set r1, 1
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.set r2, 2
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.set r3, 3
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.set r4, 4
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.set r5, 5
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.set r6, 6
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.set r7, 7
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.set r8, 8
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.set r9, 9
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.set r10, 10
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.set r11, 11
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.set r12, 12
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.set r13, 13
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.set r14, 14
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.set r15, 15
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.set r16, 16
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.set r17, 17
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.set r18, 18
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.set r19, 19
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.set r20, 20
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.set r21, 21
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.set r22, 22
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.set r23, 23
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.set r24, 24
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.set r25, 25
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.set r26, 26
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.set r27, 27
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.set r28, 28
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.set r29, 29
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.set r30, 30
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.set r31, 31
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.set f0, 0
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.set f1, 1
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.set f2, 2
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.set f3, 3
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.set f4, 4
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.set f5, 5
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.set f6, 6
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.set f7, 7
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.set f8, 8
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.set f9, 9
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.set f10, 10
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.set f11, 11
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.set f12, 12
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.set f13, 13
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.set f14, 14
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.set f15, 15
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.set f16, 16
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.set f17, 17
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.set f18, 18
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.set f19, 19
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.set f20, 20
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.set f21, 21
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.set f22, 22
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.set f23, 23
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.set f24, 24
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.set f25, 25
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.set f26, 26
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.set f27, 27
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.set f28, 28
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.set f29, 29
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.set f30, 30
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.set f31, 31
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.set qr0, 0
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.set qr1, 1
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.set qr2, 2
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.set qr3, 3
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.set qr4, 4
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.set qr5, 5
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.set qr6, 6
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.set qr7, 7
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# Gamecube Hardware Regs
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.set HW_REGS_BASE, 0xCC000000
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.set CP_REGS_BASE, 0xCC000000
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.set CP_SR, 0x00 # Status Register
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.set CP_CR, 0x02 # Control Register
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.set CP_04, 0x04 # Clear Register
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.set CP_0E, 0x0E # token register
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.set CP_10, 0x10 # bounding box - left
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.set CP_12, 0x12 # bounding box - right
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.set CP_14, 0x14 # bounding box - top
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.set CP_16, 0x16 # bounding box - bottom
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.set CP_20, 0x20 # cp FIFO base lo
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.set CP_22, 0x22 # cp FIFO base hi
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.set CP_24, 0x24 # cp FIFO end lo
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.set CP_26, 0x26 # cp FIFO end hi
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.set CP_28, 0x28 # cp FIFO high watermark lo
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.set CP_2A, 0x2A # cp FIFO high watermark hi
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.set CP_2C, 0x2C # cp FIFO low watermark lo
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.set CP_2E, 0x2E # cp FIFO low watermark hi
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.set CP_30, 0x30 # cp FIFO read/write distance lo
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.set CP_32, 0x32 # cp FIFO read/write distance hi
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.set CP_34, 0x34 # cp FIFO write pointer lo
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.set CP_36, 0x36 # cp FIFO write pointer hi
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.set CP_38, 0x38 # cp FIFO read pointer lo
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.set CP_3A, 0x3A # cp FIFO read pointer hi
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.set CP_3C, 0x3C # cp FIFO bp lo
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.set CP_3E, 0x3E # cp FIFO bp hi
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.set PE_REGS_BASE, 0xCC001000
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.set PE_00, 0x00 # Z configuration
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.set PE_02, 0x02 # Alpha configuration
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.set PE_04, 0x04 # destination alpha
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.set PE_06, 0x06 # Alpha Mode
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.set PE_08, 0x08 # Alpha Read (?)
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.set PE_0A, 0x0A # Interrupt Status Register
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.set PE_0E, 0x0E # PE Token ?
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.set VI_REGS_BASE, 0xCC002000
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.set VI_VTR, 0x00 # Vertical Timing Register
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.set VI_DCR, 0x02 # Display Configuration Register
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.set VI_HTR0, 0x04 # Horizontal Timing 0
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.set VI_06, 0x06 # ?
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.set VI_HTR1, 0x08 # Horizontal Timing 1
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.set VI_0A, 0x0A # ?
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.set VI_VTO, 0x0C # Odd Field Vertical Timing Register
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.set VI_0E, 0x0E # ?
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.set VI_VTE, 0x10 # Even Field Vertical Timing Register
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.set VI_12, 0x12 # ?
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.set VI_BBEI, 0x14 # Odd Field Burst Blanking Interval Register
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.set VI_16, 0x16 # ?
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.set VI_BBOI, 0x18 # Even Field Burst Blanking Interval Register
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.set VI_1A, 0x1A # ?
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.set VI_TFBL, 0x1C # Top Field Base Register (L) (External Framebuffer Half 1)
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.set VI_TFBR, 0x20 # Top Field Base Register (R) (Only valid in 3D Mode)
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.set VI_BFBL, 0x24 # Bottom Field Base Register (L) (External Framebuffer Half 2)
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.set VI_BFBR, 0x28 # Bottom Field Base Register (R) (Only valid in 3D Mode)
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.set VI_DPV, 0x2C # Current vertical Position
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.set VI_DPH, 0x2E # Current horizontal Position (?)
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.set VI_DI0, 0x30 # Display Interrupt 0
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.set VI_32, 0x32 # ?
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.set VI_DI1, 0x34 # DIsplay Interrupt 1
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.set VI_36, 0x36 # ?
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.set VI_DI2, 0x38 # Display Interrupt 2
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.set VI_DI3, 0x3C # Display Interrupt 3
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.set VI_DL0, 0x40 # Display Latch Register 0
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.set VI_DL1, 0x44 # Display Latch Register 1
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.set VI_HSW, 0x48 # Scaling Width Register
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.set VI_HSR, 0x4A # Horizontal Scaling Register
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.set VI_FCT0, 0x4C # Filter Coefficient Table 0 (AA stuff)
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.set VI_4E, 0x4E # ?
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.set VI_FCT1, 0x50 # Filter Coefficient Table 1 (AA stuff)
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.set VI_52, 0x52 # ?
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.set VI_FCT2, 0x54 # Filter Coefficient Table 2 (AA stuff)
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.set VI_56, 0x56 # ?
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.set VI_FCT3, 0x58 # FCT3 - Filter Coefficient Table 3 (AA stuff)
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.set VI_5A, 0x5A # ?
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.set VI_FCT4, 0x5C # FCT4 - Filter Coefficient Table 4 (AA stuff)
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.set VI_5E, 0x5E # ?
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.set VI_FCT5, 0x60 # FCT5 - Filter Coefficient Table 5 (AA stuff)
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.set VI_62, 0x62 # ?
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.set VI_FCT6, 0x64 # FCT6 - Filter Coefficient Table 6 (AA stuff)
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.set VI_66, 0x66 # ?
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.set VI_68, 0x68 # ? (AA stuff)
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.set VI_CLK, 0x6C # VI Clock Select Register
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.set VI_SEL, 0x6E # VI DTV Status Register
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.set VI_70, 0x70 # ?
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.set VI_HBE, 0x72 # Border HBE
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.set VI_HBS, 0x74 # Border HBS
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.set VI_76, 0x76 # ?
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.set VI_78, 0x78 # ?
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.set VI_7C, 0x7C # ?
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.set PI_REGS_BASE, 0xCC003000
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.set PI_INTSR, 0x00 # interrupt cause
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.set PI_INTMR, 0x04 # interrupt mask
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.set PI_0C, 0x0C # FIFO Base Start
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.set PI_10, 0x10 # FIFO Base End?
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.set PI_14, 0x14 # PI (cpu) FIFO current Write Pointer?
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.set PI_18, 0x18 # ?
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.set PI_1C, 0x1C # ?
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.set PI_20, 0x20 # ?
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.set PI_24, 0x24 # Reset?
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.set PI_2C, 0x2C # ?
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.set MI_REGS_BASE, 0xCC004000
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.set MI_00, 0x00 # Protected Region No1
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.set MI_04, 0x04 # Protected Region No2
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.set MI_08, 0x08 # Protected Region No3
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.set MI_0C, 0x0C # Protected Region No4
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.set MI_10, 0x10 # type of the protection, 4*2 bits
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.set MI_1C, 0x1C # MI interrupt mask
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.set MI_1E, 0x1E # interrupt cause
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.set MI_20, 0x20 # ?
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.set MI_22, 0x22 # ADDRLO - address which failed protection rules
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.set MI_24, 0x24 # ADDRHI - address, which failed protection rules
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.set MI_28, 0x28 # ?
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.set MI_32, 0x32 # TIMERHI
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.set MI_34, 0x34 # TIMERLO
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.set MI_36, 0x36 # TIMERHI
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.set MI_38, 0x38 # TIMERLO
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.set MI_3A, 0x3A # TIMERHI
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.set MI_3C, 0x3C # TIMERLO
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.set MI_3E, 0x3E # TIMERHI
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.set MI_40, 0x40 # TIMERLO
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.set MI_42, 0x42 # TIMERHI
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.set MI_44, 0x44 # TIMERLO
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.set MI_46, 0x46 # TIMERHI
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.set MI_48, 0x48 # TIMERLO
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.set MI_4A, 0x4A # TIMERHI
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.set MI_4C, 0x4C # TIMERLO
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.set MI_4E, 0x4E # TIMERHI
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.set MI_50, 0x50 # TIMERLO
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.set MI_52, 0x52 # TIMERHI
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.set MI_54, 0x54 # TIMERLO
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.set MI_56, 0x56 # TIMERHI
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.set MI_58, 0x58 # TIMERLO
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.set MI_5A, 0x5A # ?
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.set DSP_REGS_BASE, 0xCC005000
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.set DSP_00, 0x00 # DSP Mailbox High (to DSP)
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.set DSP_02, 0x02 # DSP Mailbox Low (to DSP)
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.set DSP_04, 0x04 # CPU Mailbox High (from DSP)
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.set DSP_06, 0x06 # CPU Mailbox Low (from DSP)
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.set DSP_0A, 0x0A # AI DSP CSR - Control Status Register (DSP Status)
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.set DSP_12, 0x12 # AR_SIZE
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.set DSP_14, 0x14 #
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.set DSP_16, 0x16 # AR_MODE
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.set DSP_1A, 0x1A # AR_REFRESH
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.set DSP_20, 0x20 # AR_DMA_MMADDR_H
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.set DSP_22, 0x22 # AR_DMA_MMADDR_L
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.set DSP_24, 0x24 # AR_DMA_ARADDR_H
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.set DSP_26, 0x26 # AR_DMA_ARADDR_L
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.set DSP_28, 0x28 # AR_DMA_CNT_H
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.set DSP_2A, 0x2A # AR_DMA_CNT_L
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.set DSP_30, 0x30 # DMA Start address (High)
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.set DSP_32, 0x32 # DMA Start address (Low)
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.set DSP_36, 0x36 # DMA Control/DMA length (Length of Audio Data)
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.set DSP_3A, 0x3A # DMA Bytes left
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.set DI_REGS_BASE, 0xCC006000
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.set DI_DISR, 0x00 # DI Status Register
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.set DI_DICVR, 0x04 # DI Cover Register (status2)
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.set DI_DICMDBUF0, 0x08 # DI Command Buffer 0
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.set DI_DICMDBUF1, 0x0C # DI Command Buffer 1 (offset in 32 bit words)
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.set DI_DICMDBUF2, 0x10 # DI Command Buffer 2 (source length)
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.set DI_DIMAR, 0x14 # DMA Memory Address Register
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.set DI_DILENGTH, 0x18 # DI DMA Transfer Length Register
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.set DI_DICR, 0x1C # DI Control Register
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.set DI_DIIMMBUF, 0x20 # DI immediate data buffer (error code ?)
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.set DI_DICFG, 0x24 # DI Configuration Register
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.set SI_REGS_BASE, 0xCC006400
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.set SI_C0OUTBUF, 0x00 # SI Channel 0 Output Buffer (Joy-channel 1 Command)
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.set SI_04, 0x04 # Joy-channel 1 Buttons 1
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.set SI_08, 0x08 # Joy-channel 1 Buttons 2
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.set SI_C1OUTBUF, 0x0C # SI Channel 1 Output Buffer (Joy-channel 2 Command)
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.set SI_C1INBUFH, 0x10 # SI Channel 1 Input Buffer High (Joy-channel 2 Buttons 1)
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.set SI_14, 0x14 # Joy-channel 2 Buttons 2
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.set SI_C2OUTBUF, 0x18 # SI Channel 2 Output Buffer (Joy-channel 3 Command)
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.set SI_1C, 0x1C # Joy-channel 3 Buttons 1
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.set SI_20, 0x20 # Joy-channel 3 Buttons 2
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.set SI_C3OUTBUF, 0x24 # SI Channel 3 Output Buffer (Joy-channel 4 Command)
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.set SI_28, 0x28 # Joy-channel 4 Buttons 1
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.set SI_C3INBUFL, 0x2C # SI Channel 3 Input Buffer Low (Joy-channel 4 Buttons 2)
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.set SI_POLL, 0x30 # SI Poll Register (Joy-channel Control (?) (Calibration gun ?))
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.set SI_COMCSR, 0x34 # SI Communication Control Status Register (command)
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.set SI_SR, 0x38 # SI Status Register (channel select & status2)
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.set SI_EXILK, 0x3C # SI EXI Clock Lock
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.set SI_IOBUF, 0x80 # SI i/o buffer (access by word)
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.set EXI_REGS_BASE, 0xCC006800
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.set EXI_00, 0x00 # EXI0CSR - EXI Channel 0 Parameter Register (Status?)
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.set EXI_04, 0x04 # EXI0MAR - EXI Channel 0 DMA Start Address
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.set EXI_08, 0x08 # EXI0LENGTH - EXI Channel 0 DMA Transfer Length
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.set EXI_0CR, 0x0C # EXI Channel 0 Control Register
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.set EXI_0DATA, 0x10 # EXI Channel 0 Immediate Data
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.set EXI_14, 0x14 # EXI1CSR - EXI Channel 1 Parameter Register
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.set EXI_18, 0x18 # EXI1MAR - EXI Channel 1 DMA Start Address
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.set EXI_1c, 0x1C # EXI Channel 1 DMA Transfer Length
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.set EXI_1CR, 0x20 # EXI Channel 1 Control Register
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.set EXI_1DATA, 0x24 # EXI Channel 1 Immediate Data
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.set EXI_28, 0x28 # EXI2CSR - EXI Channel 2 Parameter Register
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.set EXI_2c, 0x2C # EXI2MAR - EXI Channel 2 DMA Start Address
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.set EXI_30, 0x30 # EXI Channel 2 DMA Transfer Length
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.set EXI_2CR, 0x34 # EXI Channel 2 Control Register
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.set EXI_2DATA, 0x38 # EXI Channel 2 Immediate Data
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.set AI_REGS_BASE, 0xCC006C00
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.set AI_CR, 0x00 # Audio Interface Control Register
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.set AI_VR, 0x04 # Audio Interface Volume Register
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.set AI_SCNT, 0x08 # Audio Interface Sample Counter
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.set AI_IT, 0x0C # Audio Interface Interrupt Timing
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.set GX_FIFO_BASE, 0xCC008000
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