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llvm-project/llvm/test/CodeGen/AMDGPU
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Stanislav Mekhanoshin 57d341c27a [AMDGPU] Fix handling of void types in isLegalAddressingMode 
It is legal for the type passed to isLegalAddressingMode to be
unsized or, more specifically, VoidTy. In this case, we must
check the legality of load / stores for all legal types. Directly
trying to call getTypeStoreSize is incorrect, and leads to breakage
in e.g. Loop Strength Reduction. This change guards against that
behaviour.

Differential Revision: https://reviews.llvm.org/D40405

llvm-svn: 332409
2018-05-15 22:07:51 +00:00
..
GlobalISel
AMDGPU/GlobalISel: Implement select() for G_FCONSTANT
2018-05-15 17:57:09 +00:00
32-bit-local-address-space.ll
…
add_i64.ll
…
add_i128.ll
…
add-debug.ll
…
add.i16.ll
…
add.ll
…
add.v2i16.ll
[AMDGPU] Use packed literals with zero either lower or hi part
2018-04-19 21:16:50 +00:00
addrspacecast-captured.ll
…
addrspacecast-constantexpr.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
addrspacecast.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
adjust-writemask-invalid-copy.ll
…
alignbit-pat.ll
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alloca.ll
LLParser: add an argument for overriding data layout and do not check alloca addr space
2018-01-30 22:32:39 +00:00
always-uniform.ll
…
amdgcn.bitcast.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
amdgcn.private-memory.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
amdgpu-alias-analysis.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
amdgpu-codegenprepare-fdiv.ll
…
amdgpu-codegenprepare-i16-to-i32.ll
…
amdgpu-inline.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
amdgpu-shader-calling-convention.ll
…
amdgpu.private-memory.ll
AMDGPU: Fix broken dynamic vector indexing for packed types
2018-05-08 18:43:25 +00:00
amdgpu.work-item-intrinsics.deprecated.ll
…
amdpal_scratch_mergedshader.ll
[AMDGPU] Scratch setup fix on AMDPAL gfx9+ merge shader
2018-02-26 14:46:43 +00:00
amdpal-cs.ll
…
amdpal-es.ll
…
amdpal-gs.ll
…
amdpal-hs.ll
…
amdpal-ls.ll
…
amdpal-ps.ll
…
amdpal-psenable.ll
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amdpal-vs.ll
…
amdpal.ll
[AMDGPU] For OS type AMDPAL, fixed scratch on compute shader
2018-04-10 11:25:15 +00:00
and-gcn.ll
…
and.ll
…
annotate-kernel-features-hsa-call.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
annotate-kernel-features-hsa.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
annotate-kernel-features.ll
…
anonymous-gv.ll
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any_extend_vector_inreg.ll
…
anyext.ll
…
array-ptr-calc-i32.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
array-ptr-calc-i64.ll
…
ashr.v2i16.ll
[AMDGPU] Enabled v2.16 literals for VOP3P
2018-04-17 23:09:05 +00:00
atomic_cmp_swap_local.ll
…
atomic_load_add.ll
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atomic_load_sub.ll
…
attr-amdgpu-flat-work-group-size.ll
…
attr-amdgpu-num-sgpr.ll
…
attr-amdgpu-num-vgpr.ll
…
attr-amdgpu-waves-per-eu.ll
…
attr-unparseable.ll
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barrier-elimination.ll
…
basic-branch.ll
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basic-call-return.ll
AMDGPU: Fix register name format in tests
2018-03-27 18:39:42 +00:00
basic-loop.ll
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bfe_uint.ll
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bfe-combine.ll
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bfe-patterns.ll
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bfi_int.ll
AMDGPU: Select BFI patterns with 64-bit ints
2018-02-07 00:21:34 +00:00
bfm.ll
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big_alu.ll
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bitcast-vector-extract.ll
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bitreverse-inline-immediates.ll
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bitreverse.ll
DAG: Fix not truncating when promoting bswap/bitreverse
2018-01-31 23:54:16 +00:00
br_cc.f16.ll
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branch-condition-and.ll
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branch-relax-bundle.ll
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branch-relax-spill.ll
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branch-relaxation.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
branch-uniformity.ll
…
break-smem-soft-clauses.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
break-vmem-soft-clauses.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
bswap.ll
DAG: Fix not truncating when promoting bswap/bitreverse
2018-01-31 23:54:16 +00:00
buffer-schedule.ll
[AMDGPU] stop buffer_store being moved illegally
2018-02-20 10:03:38 +00:00
bug-vopc-commute.ll
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build_vector.ll
…
byval-frame-setup.ll
AMDGPU: Increase default stack alignment
2018-03-29 20:22:04 +00:00
call_fs.ll
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call-argument-types.ll
AMDGPU: Increase default stack alignment
2018-03-29 20:22:04 +00:00
call-encoding.ll
…
call-graph-register-usage.ll
AMDGPU: Increase default stack alignment
2018-03-29 20:22:04 +00:00
call-preserved-registers.ll
AMDGPU: Fix FP restore from being reordered with stack ops
2018-03-27 18:38:51 +00:00
call-return-types.ll
…
callee-frame-setup.ll
AMDGPU: Increase default stack alignment
2018-03-29 20:22:04 +00:00
callee-special-input-sgprs.ll
AMDGPU: Increase default stack alignment
2018-03-29 20:22:04 +00:00
callee-special-input-vgprs.ll
AMDGPU: Increase default stack alignment
2018-03-29 20:22:04 +00:00
calling-conventions.ll
…
captured-frame-index.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
cayman-loop-bug.ll
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cf_end.ll
…
cf-loop-on-constant.ll
[AMDGPU] Fixed incorrect uniform branch condition
2018-01-09 21:34:43 +00:00
cf-stack-bug.ll
…
cgp-addressing-modes-flat.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
cgp-addressing-modes.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
cgp-bitfield-extract.ll
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clamp-modifier.ll
[AMDGPU] Enabled v2.16 literals for VOP3P
2018-04-17 23:09:05 +00:00
clamp-omod-special-case.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
clamp.ll
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cluster-flat-loads-postra.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
cluster-flat-loads.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
cndmask-no-def-vcc.ll
[DAGCOmbine] Ensure that (brcond (setcc ...)) is handled in a canonical manner.
2018-02-23 11:50:42 +00:00
coalescer_distribute.ll
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coalescer_remat.ll
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coalescer-subrange-crash.ll
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coalescer-subreg-join.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
codegen-prepare-addrmode-sext.ll
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collapse-endcf.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
combine_vloads.ll
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combine-and-sext-bool.ll
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combine-cond-add-sub.ll
[AMDGPU] A trivial fix for a buildbot failure caused by "commit 224a839fcbbead221f872cd32a1dd0c308d37299".
2018-05-02 18:16:39 +00:00
combine-ftrunc.ll
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comdat.ll
[AMDGPU] Fix compilation failure when IR contains comdat
2018-05-11 20:40:14 +00:00
commute_modifiers.ll
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commute-compares.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
commute-shifts.ll
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complex-folding.ll
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concat_vectors.ll
[DAGCombiner] Bail out if vector size is not a multiple
2018-01-24 09:53:47 +00:00
constant-address-space-32bit.ll
Reapply "AMDGPU: Add 32-bit constant address space"
2018-02-09 16:57:57 +00:00
constant-fold-imm-immreg.mir
AMDGPU: Fix crash when constant folding with physreg operand
2018-03-10 16:05:35 +00:00
constant-fold-mi-operands.ll
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control-flow-fastregalloc.ll
[AMDGPU] Revert b0efc4fd6 (https://reviews.llvm.org/D40556)
2018-04-25 12:32:46 +00:00
control-flow-optnone.ll
Revert "StructurizeCFG: Test for branch divergence correctly"
2018-02-24 17:29:09 +00:00
convergent-inlineasm.ll
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copy-illegal-type.ll
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copy-to-reg.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
ctlz_zero_undef.ll
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ctlz.ll
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ctpop16.ll
AMDGPU/GCN: Promote i16 ctpop
2018-03-02 02:50:22 +00:00
ctpop64.ll
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ctpop.ll
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cttz_zero_undef.ll
[DAGCombiner][AMDGPU][X86] Turn cttz/ctlz into cttz_zero_undef/ctlz_zero_undef if we can prove the input is never zero
2018-02-06 23:54:37 +00:00
cube.ll
…
cvt_f32_ubyte.ll
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cvt_flr_i32_f32.ll
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cvt_rpi_i32_f32.ll
…
dagcomb-shuffle-vecextend-non2.ll
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dagcombine-reassociate-bug.ll
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dagcombiner-bug-illegal-vec4-int-to-fp.ll
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dead_copy.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
debug-value2.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
debug-value.ll
[AMDGPU] fix test to survive more FP undef constant folding
2018-03-08 21:30:56 +00:00
debug.ll
…
debugger-emit-prologue.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
debugger-insert-nops.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
debugger-reserve-regs.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
default-fp-mode.ll
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detect-dead-lanes.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
disconnected-predset-break-bug.ll
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diverge-extra-formal-args.ll
[AMDGPU] Fix issues for backend divergence tracking
2018-04-18 13:53:31 +00:00
diverge-interp-mov-lower.ll
[AMDGPU] Fix issues for backend divergence tracking
2018-04-18 13:53:31 +00:00
drop-mem-operand-move-smrd.ll
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ds_read2_offset_order.ll
…
ds_read2_superreg.ll
…
ds_read2.ll
AMDGPU: Track physreg uses in SILoadStoreOptimizer
2018-02-23 10:45:56 +00:00
ds_read2st64.ll
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ds_write2.ll
…
ds_write2st64.ll
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ds-combine-large-stride.ll
[AMDGPU] SI Load Store Optimizer: When merging with offset, use V_ADD_{I|U}32_e64
2018-01-22 21:46:43 +00:00
ds-negative-offset-addressing-mode-loop.ll
…
ds-sub-offset.ll
…
dynamic_stackalloc.ll
…
early-if-convert-cost.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
early-if-convert.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
early-inline-alias.ll
…
early-inline.ll
…
elf-header-flags-mach.ll
AMDGPU: Add Vega12 and Vega20
2018-04-30 19:08:16 +00:00
elf-header-flags-xnack.ll
AMDGPU: Bring elf flags in sync with the spec
2018-02-16 22:33:59 +00:00
elf-header-osabi.ll
AMDGPU: Bring elf flags in sync with the spec
2018-02-16 22:33:59 +00:00
elf-notes.ll
AMDGPU: Bring processors and features in sync with the spec
2018-02-16 21:26:25 +00:00
elf.ll
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elf.r600.ll
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else.ll
…
empty-function.ll
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enable-no-signed-zeros-fp-math.ll
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endcf-loop-header.ll
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endpgm-dce.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
enqueue-kernel.ll
[AMDGPU] Fix lowering enqueue_kernel
2018-04-11 14:46:15 +00:00
env-amdgiz.ll
…
env-amdgizcl.ll
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exceed-max-sgprs.ll
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extend-bit-ops-i16.ll
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extload-align.ll
[CodeGen] Use MIR syntax for MachineMemOperand printing
2018-03-14 21:52:13 +00:00
extload-private.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
extload.ll
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extract_vector_elt-f16.ll
AMDGPU: Fix broken dynamic vector indexing for packed types
2018-05-08 18:43:25 +00:00
extract_vector_elt-f64.ll
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extract_vector_elt-i8.ll
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extract_vector_elt-i16.ll
AMDGPU: Fix broken dynamic vector indexing for packed types
2018-05-08 18:43:25 +00:00
extract_vector_elt-i64.ll
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extract-vector-elt-build-vector-combine.ll
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extractelt-to-trunc.ll
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fabs.f16.ll
AMDGPU: Extend extract_vector_elt fneg combine to fabs
2018-04-26 19:21:32 +00:00
fabs.f64.ll
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fabs.ll
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fadd64.ll
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fadd-fma-fmul-combine.ll
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fadd.f16.ll
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fadd.ll
…
fcanonicalize-elimination.ll
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fcanonicalize.f16.ll
[AMDGPU] Enabled v2.16 literals for VOP3P
2018-04-17 23:09:05 +00:00
fcanonicalize.ll
DAG: Fix not legalizing vector fcanonicalizes
2018-04-26 19:21:37 +00:00
fceil64.ll
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fceil.ll
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fcmp64.ll
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fcmp-cnd.ll
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fcmp-cnde-int-args.ll
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fcmp.f16.ll
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fcmp.ll
…
fconst64.ll
…
fcopysign.f16.ll
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fcopysign.f32.ll
…
fcopysign.f64.ll
…
fdiv.f16.ll
[AMDGPU] Fixed V_DIV_FIXUP_F16 selection on GFX9
2018-03-09 07:21:43 +00:00
fdiv.f64.ll
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fdiv.ll
…
fence-amdgiz.ll
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fence-barrier.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
fetch-limits.r600.ll
…
fetch-limits.r700+.ll
…
ffloor.f64.ll
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ffloor.ll
…
fix-vgpr-copies.mir
Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
2018-02-27 16:59:10 +00:00
fix-wwm-liveness.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
flat_atomics_i64.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
flat_atomics.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
flat-address-space.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
flat-for-global-subtarget-feature.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
flat-load-clustering.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
flat-scratch-reg.ll
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floor.ll
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fma-combine.ll
…
fma.f64.ll
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fma.ll
AMDGPU: Add Vega12 and Vega20
2018-04-30 19:08:16 +00:00
fmad.ll
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fmax3.f64.ll
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fmax3.ll
[AMDGPU] performMinMaxCombine should not optimize patterns of vectors to min3/max3.
2018-04-03 23:00:30 +00:00
fmax_legacy.f64.ll
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fmax_legacy.ll
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fmax.ll
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fmaxnum.f64.ll
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fmaxnum.ll
…
fmed3.ll
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fmin3.ll
[AMDGPU] performMinMaxCombine should not optimize patterns of vectors to min3/max3.
2018-04-03 23:00:30 +00:00
fmin_fmax_legacy.amdgcn.ll
…
fmin_legacy.f64.ll
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fmin_legacy.ll
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fmin.ll
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fminnum.f64.ll
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fminnum.ll
…
fmul64.ll
…
fmul-2-combine-multi-use.ll
…
fmul.f16.ll
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fmul.ll
…
fmuladd.f16.ll
[AMDGPU] Removed redundant run lines for fmuladd.f16 test. NFC.
2018-02-20 19:19:56 +00:00
fmuladd.f32.ll
AMDGPU: Add Vega12 and Vega20
2018-04-30 19:08:16 +00:00
fmuladd.f64.ll
…
fmuladd.v2f16.ll
[AMDGPU] Enabled v2.16 literals for VOP3P
2018-04-17 23:09:05 +00:00
fnearbyint.ll
…
fneg-combines.ll
…
fneg-fabs.f16.ll
[AMDGPU] Enabled v2.16 literals for VOP3P
2018-04-17 23:09:05 +00:00
fneg-fabs.f64.ll
…
fneg-fabs.ll
…
fneg.f16.ll
…
fneg.f64.ll
…
fneg.ll
…
fold-cndmask.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
fold-fmul-to-neg-abs.ll
…
fold-imm-f16-f32.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
fold-immediate-output-mods.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
fold-implicit-operand.mir
AMDGPU: Don't crash when trying to fold implicit operands
2018-02-08 01:12:46 +00:00
fold-multiple.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
fold-operands-order.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
fp16_to_fp32.ll
…
fp16_to_fp64.ll
…
fp32_to_fp16.ll
…
fp_to_sint.f64.ll
…
fp_to_sint.ll
…
fp_to_uint.f64.ll
…
fp_to_uint.ll
…
fp-classify.ll
…
fpext-free.ll
…
fpext.f16.ll
…
fpext.ll
…
fptosi.f16.ll
…
fptoui.f16.ll
…
fptrunc.f16.ll
…
fptrunc.ll
…
fract.f64.ll
…
fract.ll
…
frame-index-amdgiz.ll
…
frame-index-elimination.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
frem.ll
…
fsqrt.f64.ll
…
fsqrt.ll
…
fsub64.ll
…
fsub.f16.ll
…
fsub.ll
…
ftrunc.f64.ll
…
ftrunc.ll
…
function-args.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
function-returns.ll
AMDGPU: Add combine for trunc of bitcast from build_vector
2018-05-09 18:37:39 +00:00
gep-address-space.ll
…
global_atomics_i64.ll
…
global_atomics.ll
…
global_smrd_cfg.ll
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global_smrd.ll
…
global-constant.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
global-directive.ll
…
global-extload-i16.ll
…
global-smrd-unknown.ll
AMDGPU: Don't use undef in a test
2018-05-08 18:43:34 +00:00
global-variable-relocs.ll
…
gv-const-addrspace.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
gv-offset-folding.ll
…
half.ll
…
hazard-inlineasm.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
hazard.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
hoist-cond.ll
…
hsa-default-device.ll
…
hsa-fp-mode.ll
…
hsa-func-align.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
hsa-func.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
hsa-globals.ll
…
hsa-group-segment.ll
…
hsa-metadata-deduce-ro-arg.ll
…
hsa-metadata-enqueu-kernel.ll
AMDGPU/Metadata: Always report a fixed number of hidden arguments
2018-04-05 20:46:04 +00:00
hsa-metadata-from-llvm-ir-full.ll
AMDGPU: Bring processors and features in sync with the spec
2018-02-16 21:26:25 +00:00
hsa-metadata-hidden-args.ll
AMDGPU/Metadata: Always report a fixed number of hidden arguments
2018-04-05 20:46:04 +00:00
hsa-metadata-images.ll
AMDGPU: Bring processors and features in sync with the spec
2018-02-16 21:26:25 +00:00
hsa-metadata-invalid-ocl-version-1.ll
…
hsa-metadata-invalid-ocl-version-2.ll
…
hsa-metadata-invalid-ocl-version-3.ll
…
hsa-metadata-kernel-code-props.ll
…
hsa-metadata-kernel-debug-props.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
hsa-note-no-func.ll
AMDGPU: Add Vega12 and Vega20
2018-04-30 19:08:16 +00:00
hsa.ll
…
huge-private-buffer.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
i1-copy-from-loop.ll
AMDGPU: Fix copying i1 value out of loop with non-uniform exit
2018-04-04 10:57:58 +00:00
i1-copy-implicit-def.ll
…
i1-copy-phi.ll
…
i8-to-double-to-float.ll
…
icmp64.ll
…
icmp-select-sete-reverse-args.ll
…
icmp.i16.ll
…
illegal-sgpr-to-vgpr-copy.ll
…
image-attributes.ll
…
image-resource-id.ll
…
image-schedule.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
imm16.ll
[AMDGPU] adjust tests to be nan-free
2018-03-19 19:23:53 +00:00
imm.ll
[InstSimplify] fp_binop X, NaN --> NaN
2018-03-21 19:31:53 +00:00
immv216.ll
[AMDGPU] Use packed literals with zero either lower or hi part
2018-04-19 21:16:50 +00:00
indirect-addressing-si-noopt.ll
…
indirect-addressing-si.ll
AMDGPU/SI: Turn off GPR Indexing Mode immediately after the interested instruction.
2018-02-16 16:31:30 +00:00
indirect-private-64.ll
AMDGPU/SI: Extend promoting alloca to vector to arrays of up to 16 elements
2018-02-16 19:14:17 +00:00
infer-addrpace-pipeline.ll
…
infinite-loop-evergreen.ll
…
infinite-loop.ll
…
inline-asm.ll
…
inline-attr.ll
…
inline-calls.ll
…
inline-constraints.ll
…
inlineasm-16.ll
…
inlineasm-illegal-type.ll
…
inlineasm-packed.ll
…
InlineAsmCrash.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
input-mods.ll
…
insert_subreg.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
insert_vector_elt.ll
[AMDGPU][Waitcnt] As of gfx7, VMEM operations do not increment the export counter and the input registers are available in the next instruction; update the waitcnt pass to take this into account.
2018-04-26 16:11:19 +00:00
insert_vector_elt.v2i16.ll
AMDGPU: Fix broken dynamic vector indexing for packed types
2018-05-08 18:43:25 +00:00
insert-skips-kill-uncond.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
insert-waitcnts-callee.mir
[AMDGPU][Waitcnt] Update a few tests to use default waitcnt pass (si-insert-waitcnts) rather than old pass (si-insert-waits); this is a small step towards the overall goal of removing the old waitcnt pass, which is no longer maintained.
2018-04-27 17:59:15 +00:00
insert-waitcnts-exp.mir
[AMDGPU][Waitcnt] Update a few tests to use default waitcnt pass (si-insert-waitcnts) rather than old pass (si-insert-waits); this is a small step towards the overall goal of removing the old waitcnt pass, which is no longer maintained.
2018-04-27 17:59:15 +00:00
inserted-wait-states.mir
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
internalize.ll
…
invalid-addrspacecast.ll
…
invalid-alloca.ll
LLParser: add an argument for overriding data layout and do not check alloca addr space
2018-01-30 22:32:39 +00:00
invariant-load-no-alias-store.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
invert-br-undef-vcc.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
ipra.ll
…
jump-address.ll
[AMDGPU] change test to avoid NaN math
2018-03-19 19:26:22 +00:00
kcache-fold.ll
…
kernarg-stack-alignment.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
kernel-args.ll
[AMDGPU] Remove non-temporal flag from argument loads
2018-02-14 18:05:14 +00:00
knownbits-recursion.ll
…
large-alloca-compute.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
large-alloca-graphics.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
large-constant-initializer.ll
…
large-work-group-promote-alloca.ll
AMDGPU/SI: Extend promoting alloca to vector to arrays of up to 16 elements
2018-02-16 19:14:17 +00:00
lds_atomic_f32.ll
[AMDGPU] fix LDS f32 intrinsics
2018-01-26 11:09:38 +00:00
lds-alignment.ll
[NFC] fix trivial typos in comments and documents
2018-01-29 05:17:03 +00:00
lds-initializer.ll
…
lds-m0-init-in-loop.ll
…
lds-oqap-crash.ll
…
lds-output-queue.ll
…
lds-size.ll
…
lds-zero-initializer.ll
…
legalizedag-bug-expand-setcc.ll
…
limit-coalesce.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
lit.local.cfg
…
literals.ll
…
liveness.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
llvm.amdgcn.alignb.ll
…
llvm.amdgcn.atomic.dec.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
llvm.amdgcn.atomic.inc.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
llvm.amdgcn.buffer.atomic.ll
…
llvm.amdgcn.buffer.load.format.d16.ll
AMDGPU/SI: Adjust the encoding family for D16 buffer instructions when the target has UnpackedD16VMem feature.
2018-02-01 18:41:33 +00:00
llvm.amdgcn.buffer.load.format.ll
…
llvm.amdgcn.buffer.load.ll
…
llvm.amdgcn.buffer.store.format.d16.ll
[AMDGPU] Remove non-temporal flag from argument loads
2018-02-14 18:05:14 +00:00
llvm.amdgcn.buffer.store.format.ll
[AMDGPU][Waitcnt] As of gfx7, VMEM operations do not increment the export counter and the input registers are available in the next instruction; update the waitcnt pass to take this into account.
2018-04-26 16:11:19 +00:00
llvm.amdgcn.buffer.store.ll
[AMDGPU][Waitcnt] As of gfx7, VMEM operations do not increment the export counter and the input registers are available in the next instruction; update the waitcnt pass to take this into account.
2018-04-26 16:11:19 +00:00
llvm.amdgcn.buffer.wbinvl1.ll
…
llvm.amdgcn.buffer.wbinvl1.sc.ll
…
llvm.amdgcn.buffer.wbinvl1.vol.ll
…
llvm.amdgcn.class.f16.ll
…
llvm.amdgcn.class.ll
…
llvm.amdgcn.cos.f16.ll
…
llvm.amdgcn.cos.ll
…
llvm.amdgcn.cubeid.ll
…
llvm.amdgcn.cubema.ll
…
llvm.amdgcn.cubesc.ll
…
llvm.amdgcn.cubetc.ll
…
llvm.amdgcn.cvt.pk.i16.ll
AMDGPU: Add intrinsics llvm.amdgcn.cvt.{pknorm.i16, pknorm.u16, pk.i16, pk.u16}
2018-01-31 20:18:04 +00:00
llvm.amdgcn.cvt.pk.u16.ll
AMDGPU: Add intrinsics llvm.amdgcn.cvt.{pknorm.i16, pknorm.u16, pk.i16, pk.u16}
2018-01-31 20:18:04 +00:00
llvm.amdgcn.cvt.pknorm.i16.ll
AMDGPU: Add intrinsics llvm.amdgcn.cvt.{pknorm.i16, pknorm.u16, pk.i16, pk.u16}
2018-01-31 20:18:04 +00:00
llvm.amdgcn.cvt.pknorm.u16.ll
AMDGPU: Add intrinsics llvm.amdgcn.cvt.{pknorm.i16, pknorm.u16, pk.i16, pk.u16}
2018-01-31 20:18:04 +00:00
llvm.amdgcn.cvt.pkrtz.ll
AMDGPU: Make undef legal for v2i16/v2f16
2018-05-13 10:04:38 +00:00
llvm.amdgcn.dispatch.id.ll
…
llvm.amdgcn.dispatch.ptr.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
llvm.amdgcn.div.fixup.f16.ll
…
llvm.amdgcn.div.fixup.ll
…
llvm.amdgcn.div.fmas.ll
…
llvm.amdgcn.div.scale.ll
…
llvm.amdgcn.ds.bpermute.ll
…
llvm.amdgcn.ds.permute.ll
…
llvm.amdgcn.ds.swizzle.ll
…
llvm.amdgcn.exp.compr.ll
…
llvm.amdgcn.exp.ll
…
llvm.amdgcn.fcmp.ll
…
llvm.amdgcn.fdiv.fast.ll
…
llvm.amdgcn.fdot2.ll
AMDGPU: Add Vega12 and Vega20
2018-04-30 19:08:16 +00:00
llvm.amdgcn.fmed3.f16.ll
…
llvm.amdgcn.fmed3.ll
…
llvm.amdgcn.fmul.legacy.ll
…
llvm.amdgcn.fract.f16.ll
…
llvm.amdgcn.fract.ll
…
llvm.amdgcn.frexp.exp.f16.ll
…
llvm.amdgcn.frexp.exp.ll
…
llvm.amdgcn.frexp.mant.f16.ll
…
llvm.amdgcn.frexp.mant.ll
…
llvm.amdgcn.groupstaticsize.ll
…
llvm.amdgcn.icmp.ll
…
llvm.amdgcn.image.atomic.dim.ll
AMDGPU: Dimension-aware image intrinsics
2018-04-04 10:58:54 +00:00
llvm.amdgcn.image.atomic.ll
…
llvm.amdgcn.image.d16.dim.ll
AMDGPU: Dimension-aware image intrinsics
2018-04-04 10:58:54 +00:00
llvm.amdgcn.image.d16.ll
[AMDGPU] Remove non-temporal flag from argument loads
2018-02-14 18:05:14 +00:00
llvm.amdgcn.image.dim.ll
AMDGPU: Dimension-aware image intrinsics
2018-04-04 10:58:54 +00:00
llvm.amdgcn.image.gather4.d16.dim.ll
AMDGPU: Dimension-aware image intrinsics
2018-04-04 10:58:54 +00:00
llvm.amdgcn.image.gather4.d16.ll
AMDGPU: Add combine for trunc of bitcast from build_vector
2018-05-09 18:37:39 +00:00
llvm.amdgcn.image.gather4.dim.ll
AMDGPU: Dimension-aware image intrinsics
2018-04-04 10:58:54 +00:00
llvm.amdgcn.image.gather4.ll
[AMDGPU][MC] Corrected GATHER4 opcodes
2018-03-12 15:03:34 +00:00
llvm.amdgcn.image.getlod.ll
…
llvm.amdgcn.image.ll
[AMDGPU][Waitcnt] As of gfx7, VMEM operations do not increment the export counter and the input registers are available in the next instruction; update the waitcnt pass to take this into account.
2018-04-26 16:11:19 +00:00
llvm.amdgcn.image.sample.d16.dim.ll
AMDGPU: Dimension-aware image intrinsics
2018-04-04 10:58:54 +00:00
llvm.amdgcn.image.sample.d16.ll
AMDGPU: Add combine for trunc of bitcast from build_vector
2018-05-09 18:37:39 +00:00
llvm.amdgcn.image.sample.dim.ll
AMDGPU: Dimension-aware image intrinsics
2018-04-04 10:58:54 +00:00
llvm.amdgcn.image.sample.ll
…
llvm.amdgcn.image.sample.o.ll
…
llvm.amdgcn.implicit.buffer.ptr.hsa.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
llvm.amdgcn.implicit.buffer.ptr.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
llvm.amdgcn.implicitarg.ptr.ll
[AMDGPU] Update OpenCL to use 48 bytes of implicit arguments for AMDGPU
2018-03-23 18:58:47 +00:00
llvm.amdgcn.init.exec.ll
AMDGPU: Fix a corner case crash in SIOptimizeExecMasking
2018-04-23 13:05:50 +00:00
llvm.amdgcn.interp.ll
[AMDGPU][MC][GFX8][GFX9][DISASSEMBLER] Added "_e32" suffix to 32-bit VINTRP opcodes
2018-03-16 16:38:04 +00:00
llvm.amdgcn.kernarg.segment.ptr.ll
[AMDGPU] Update OpenCL to use 48 bytes of implicit arguments for AMDGPU
2018-03-23 18:58:47 +00:00
llvm.amdgcn.kill.ll
AMDGPU: Allow a SGPR for the conditional KILL operand
2018-01-29 23:19:10 +00:00
llvm.amdgcn.ldexp.f16.ll
…
llvm.amdgcn.ldexp.ll
…
llvm.amdgcn.lerp.ll
…
llvm.amdgcn.log.clamp.ll
…
llvm.amdgcn.mbcnt.ll
…
llvm.amdgcn.mov.dpp.ll
…
llvm.amdgcn.mqsad.pk.u16.u8.ll
…
llvm.amdgcn.mqsad.u32.u8.ll
…
llvm.amdgcn.msad.u8.ll
…
llvm.amdgcn.ps.live.ll
…
llvm.amdgcn.qsad.pk.u16.u8.ll
…
llvm.amdgcn.queue.ptr.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
llvm.amdgcn.rcp.f16.ll
…
llvm.amdgcn.rcp.legacy.ll
…
llvm.amdgcn.rcp.ll
…
llvm.amdgcn.readfirstlane.ll
…
llvm.amdgcn.readlane.ll
…
llvm.amdgcn.rsq.clamp.ll
…
llvm.amdgcn.rsq.f16.ll
…
llvm.amdgcn.rsq.legacy.ll
…
llvm.amdgcn.rsq.ll
…
llvm.amdgcn.s.barrier.ll
…
llvm.amdgcn.s.dcache.inv.ll
…
llvm.amdgcn.s.dcache.inv.vol.ll
…
llvm.amdgcn.s.dcache.wb.ll
…
llvm.amdgcn.s.dcache.wb.vol.ll
…
llvm.amdgcn.s.decperflevel.ll
…
llvm.amdgcn.s.getpc.ll
…
llvm.amdgcn.s.getreg.ll
…
llvm.amdgcn.s.incperflevel.ll
…
llvm.amdgcn.s.memrealtime.ll
…
llvm.amdgcn.s.memtime.ll
…
llvm.amdgcn.s.sleep.ll
…
llvm.amdgcn.s.waitcnt.ll
[AMDGPU] Combine adjacent waitcounts in a single strongest wait
2018-02-15 22:03:55 +00:00
llvm.amdgcn.sad.hi.u8.ll
…
llvm.amdgcn.sad.u8.ll
…
llvm.amdgcn.sad.u16.ll
…
llvm.amdgcn.sbfe.ll
…
llvm.amdgcn.sdot2.ll
AMDGPU: Add Vega12 and Vega20
2018-04-30 19:08:16 +00:00
llvm.amdgcn.sdot4.ll
AMDGPU: Add Vega12 and Vega20
2018-04-30 19:08:16 +00:00
llvm.amdgcn.sdot8.ll
AMDGPU: Add Vega12 and Vega20
2018-04-30 19:08:16 +00:00
llvm.amdgcn.sendmsg.ll
AMDGPU: Legalize the operand of SI_INIT_M0
2018-04-20 07:14:25 +00:00
llvm.amdgcn.set.inactive.ll
…
llvm.amdgcn.sffbh.ll
…
llvm.amdgcn.sin.f16.ll
…
llvm.amdgcn.sin.ll
…
llvm.amdgcn.tbuffer.load.d16.ll
AMDGPU/SI: Adjust the encoding family for D16 buffer instructions when the target has UnpackedD16VMem feature.
2018-02-01 18:41:33 +00:00
llvm.amdgcn.tbuffer.load.ll
…
llvm.amdgcn.tbuffer.store.d16.ll
[AMDGPU] Remove non-temporal flag from argument loads
2018-02-14 18:05:14 +00:00
llvm.amdgcn.tbuffer.store.ll
[AMDGPU][Waitcnt] As of gfx7, VMEM operations do not increment the export counter and the input registers are available in the next instruction; update the waitcnt pass to take this into account.
2018-04-26 16:11:19 +00:00
llvm.amdgcn.trig.preop.ll
…
llvm.amdgcn.ubfe.ll
…
llvm.amdgcn.udot2.ll
AMDGPU: Add Vega12 and Vega20
2018-04-30 19:08:16 +00:00
llvm.amdgcn.udot4.ll
AMDGPU: Add Vega12 and Vega20
2018-04-30 19:08:16 +00:00
llvm.amdgcn.udot8.ll
AMDGPU: Add Vega12 and Vega20
2018-04-30 19:08:16 +00:00
llvm.amdgcn.unreachable.ll
…
llvm.amdgcn.update.dpp.ll
…
llvm.amdgcn.wave.barrier.ll
…
llvm.amdgcn.workgroup.id.ll
…
llvm.amdgcn.workitem.id.ll
…
llvm.amdgcn.wqm.vote.ll
…
llvm.amdgcn.writelane.ll
[AMDGPU] added writelane intrinsic
2018-02-28 19:10:32 +00:00
llvm.AMDGPU.kill.ll
…
llvm.ceil.f16.ll
…
llvm.cos.f16.ll
…
llvm.cos.ll
…
llvm.dbg.value.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
llvm.exp2.f16.ll
[AMDGPU] Fixed some instructions latencies
2018-03-30 16:19:13 +00:00
llvm.exp2.ll
…
llvm.floor.f16.ll
…
llvm.fma.f16.ll
…
llvm.fmuladd.f16.ll
…
llvm.log2.f16.ll
…
llvm.log2.ll
…
llvm.log10.f16.ll
…
llvm.log10.ll
…
llvm.log.f16.ll
…
llvm.log.ll
…
llvm.maxnum.f16.ll
…
llvm.memcpy.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
llvm.minnum.f16.ll
…
llvm.pow.ll
…
llvm.r600.cube.ll
…
llvm.r600.dot4.ll
…
llvm.r600.group.barrier.ll
…
llvm.r600.read.local.size.ll
…
llvm.r600.recipsqrt.clamped.ll
…
llvm.r600.recipsqrt.ieee.ll
…
llvm.r600.tex.ll
…
llvm.rint.f16.ll
…
llvm.rint.f64.ll
…
llvm.rint.ll
…
llvm.round.f64.ll
…
llvm.round.ll
…
llvm.SI.load.dword.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
llvm.SI.tbuffer.store.ll
…
llvm.sin.f16.ll
…
llvm.sin.ll
…
llvm.sqrt.f16.ll
[AMDGPU] Fixed some instructions latencies
2018-03-30 16:19:13 +00:00
llvm.trunc.f16.ll
…
load-constant-f32.ll
[AMDGPU] Increased vector length for global/constant loads.
2018-03-07 17:09:18 +00:00
load-constant-f64.ll
[AMDGPU] Increased vector length for global/constant loads.
2018-03-07 17:09:18 +00:00
load-constant-i1.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
load-constant-i8.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
load-constant-i16.ll
AMDGPU: Fix selection error on constant loads with < 4 byte alignment
2018-03-29 19:59:28 +00:00
load-constant-i32.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
load-constant-i64.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
load-global-f32.ll
…
load-global-f64.ll
…
load-global-i1.ll
…
load-global-i8.ll
…
load-global-i16.ll
AMDGPU: Fix selection error on constant loads with < 4 byte alignment
2018-03-29 19:59:28 +00:00
load-global-i32.ll
…
load-global-i64.ll
…
load-hi16.ll
AMDGPU: Add D16 instructions preserve unused bits feature
2018-05-04 20:06:57 +00:00
load-input-fold.ll
…
load-lo16.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
load-local-f32-no-ds128.ll
AMDGPU: Add a missing test for the 128-bit local addr space option
2018-05-15 21:41:57 +00:00
load-local-f32.ll
AMDGPU: enable 128-bit for local addr space under an option
2018-04-10 22:48:23 +00:00
load-local-f64.ll
AMDGPU: enable 128-bit for local addr space under an option
2018-04-10 22:48:23 +00:00
load-local-i1.ll
…
load-local-i8.ll
AMDGPU: enable 128-bit for local addr space under an option
2018-04-10 22:48:23 +00:00
load-local-i16.ll
AMDGPU: enable 128-bit for local addr space under an option
2018-04-10 22:48:23 +00:00
load-local-i32.ll
AMDGPU: enable 128-bit for local addr space under an option
2018-04-10 22:48:23 +00:00
load-local-i64.ll
AMDGPU: enable 128-bit for local addr space under an option
2018-04-10 22:48:23 +00:00
load-private-double16-amdgiz.ll
…
load-select-ptr.ll
AMDGPU: Fix crash when MachinePointerInfo invalid
2018-03-27 18:39:45 +00:00
load-weird-sizes.ll
…
local-64.ll
…
local-atomics64.ll
…
local-atomics.ll
…
local-memory.amdgcn.ll
…
local-memory.ll
…
local-memory.r600.ll
…
local-stack-slot-offset.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
loop_break.ll
…
loop-address.ll
…
loop-idiom.ll
…
lower-mem-intrinsics.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
lower-range-metadata-intrinsic-call.ll
…
lshl64-to-32.ll
…
lshr.v2i16.ll
[AMDGPU] Enabled v2.16 literals for VOP3P
2018-04-17 23:09:05 +00:00
lsr-void.ll
[AMDGPU] Fix handling of void types in isLegalAddressingMode
2018-05-15 22:07:51 +00:00
macro-fusion-cluster-vcc-uses.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
mad24-get-global-id.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
mad_64_32.ll
[AMDGPU] Fixed some instructions latencies
2018-03-30 16:19:13 +00:00
mad_int24.ll
…
mad_uint24.ll
…
mad-combine.ll
…
mad-mix-hi.ll
…
mad-mix-lo.ll
…
mad-mix.ll
AMDGPU: Add Vega12 and Vega20
2018-04-30 19:08:16 +00:00
madak.ll
[AMDGPU] Fixed madak.ll test on VI, added GFX10. NFC.
2018-02-23 23:53:27 +00:00
madmk.ll
[AMDGPU] fix tests to be independent of FP undef
2018-03-10 16:39:59 +00:00
max3.ll
…
max-literals.ll
…
max.i16.ll
…
max.ll
…
mem-builtins.ll
…
memory-legalizer-atomic-cmpxchg.ll
[AMDGPU] Cleanup in memory legalizer tests. NFC.
2018-02-13 20:03:32 +00:00
memory-legalizer-atomic-fence.ll
[AMDGPU] Cleanup in memory legalizer tests. NFC.
2018-02-13 20:03:32 +00:00
memory-legalizer-atomic-insert-end.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
memory-legalizer-atomic-rmw.ll
[AMDGPU] Cleanup in memory legalizer tests. NFC.
2018-02-13 20:03:32 +00:00
memory-legalizer-invalid-syncscope.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
memory-legalizer-load.ll
[AMDGPU] Cleanup in memory legalizer tests. NFC.
2018-02-13 20:03:32 +00:00
memory-legalizer-multiple-mem-operands-atomics.mir
[MIR] Add support for debug metadata for fixed stack objects
2018-04-25 18:58:06 +00:00
memory-legalizer-multiple-mem-operands-nontemporal-1.mir
[MIR] Add support for debug metadata for fixed stack objects
2018-04-25 18:58:06 +00:00
memory-legalizer-multiple-mem-operands-nontemporal-2.mir
[MIR] Add support for debug metadata for fixed stack objects
2018-04-25 18:58:06 +00:00
memory-legalizer-store-infinite-loop.ll
…
memory-legalizer-store.ll
[AMDGPU] Cleanup in memory legalizer tests. NFC.
2018-02-13 20:03:32 +00:00
merge-load-store-physreg.mir
AMDGPU: Track physreg uses in SILoadStoreOptimizer
2018-02-23 10:45:56 +00:00
merge-load-store-vreg.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
merge-load-store.mir
AMDGPU: Fix incorrect reordering when inline asm defines LDS address
2018-02-08 01:56:14 +00:00
merge-m0.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
merge-store-crash.ll
…
merge-store-usedef.ll
…
merge-stores.ll
…
mesa_regression.ll
…
min3.ll
…
min.ll
…
misched-killflags.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
missing-store.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
move-addr64-rsrc-dead-subreg-writes.ll
…
move-to-valu-atomicrmw.ll
…
move-to-valu-worklist.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
movreld-bug.ll
…
movrels-bug.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
mubuf-offset-private.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
mubuf-shader-vgpr.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
mubuf.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
mul_int24.ll
…
mul_uint24-amdgcn.ll
AMDGPU: Ignore any_extend in mul24 combine
2018-05-09 21:11:35 +00:00
mul_uint24-r600.ll
…
mul.ll
[AMDGPU] Fixed some instructions latencies
2018-03-30 16:19:13 +00:00
multi-divergent-exit-region.ll
[AMDGPU] Don't force WQM for DS op
2018-05-07 13:21:26 +00:00
multilevel-break.ll
Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
2018-02-27 16:59:10 +00:00
nested-calls.ll
AMDGPU: Increase default stack alignment
2018-03-29 20:22:04 +00:00
nested-loop-conditions.ll
Revert r321751, "StructurizeCFG: Fix broken backedge detection"
2018-01-24 18:02:05 +00:00
no-hsa-graphics-shaders.ll
…
no-initializer-constant-addrspace.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
no-shrink-extloads.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
nop-data.ll
…
not-scalarize-volatile-load.ll
…
nullptr.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
omod.ll
…
opencl-image-metadata.ll
…
operand-folding.ll
…
operand-spacing.ll
…
opt-sgpr-to-vgpr-copy.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
optimize-if-exec-masking.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
or.ll
…
over-max-lds-size.ll
…
pack.v2f16.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
pack.v2i16.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
packed-op-sel.ll
…
packetizer.ll
…
parallelandifcollapse.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
parallelorifcollapse.ll
…
partial-sgpr-to-vgpr-spills.ll
…
partial-shift-shrink.ll
AMDGPU: Handle partial shift reduction for variable shifts
2018-05-09 20:52:54 +00:00
partially-dead-super-register-immediate.ll
…
pk_max_f16_literal.ll
[AMDGPU] Truncate packed inline constant
2018-04-24 18:17:55 +00:00
postra-norename.mir
[MachineOperand][Target] MachineOperand::isRenamable semantics changes
2018-02-23 18:25:08 +00:00
predicate-dp4.ll
…
predicates.ll
…
print-mir-custom-pseudo.ll
[CodeGen] Fixed unreachable with -print-machineinstrs and custom pseudo source value
2018-03-27 21:14:04 +00:00
private-access-no-objects.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
private-element-size.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
private-memory-atomics.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
private-memory-r600.ll
AMDGPU/SI: Extend promoting alloca to vector to arrays of up to 16 elements
2018-02-16 19:14:17 +00:00
promote-alloca-addrspacecast.ll
…
promote-alloca-array-aggregate.ll
…
promote-alloca-array-allocation.ll
…
promote-alloca-bitcast-function.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
promote-alloca-calling-conv.ll
AMDGPU: Increase default stack alignment
2018-03-29 20:22:04 +00:00
promote-alloca-globals.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
promote-alloca-invariant-markers.ll
Rename invariant.group.barrier to launder.invariant.group
2018-05-03 11:03:01 +00:00
promote-alloca-lifetime.ll
…
promote-alloca-mem-intrinsics.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
promote-alloca-no-opts.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
promote-alloca-padding-size-estimate.ll
AMDGPU/SI: Extend promoting alloca to vector to arrays of up to 16 elements
2018-02-16 19:14:17 +00:00
promote-alloca-stored-pointer-value.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
promote-alloca-to-lds-icmp.ll
…
promote-alloca-to-lds-phi.ll
…
promote-alloca-to-lds-select.ll
…
promote-alloca-unhandled-intrinsic.ll
…
promote-alloca-volatile.ll
…
pv-packing.ll
…
pv.ll
…
r600-constant-array-fixup.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
r600-encoding.ll
…
r600-export-fix.ll
…
r600-infinite-loop-bug-while-reorganizing-vector.ll
…
r600-legalize-umax-bug.ll
…
r600.alu-limits.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
r600.amdgpu-alias-analysis.ll
…
r600.bitcast.ll
…
r600.global_atomics.ll
…
r600.private-memory.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
r600.work-item-intrinsics.ll
[SelectionDAG] Provide adequate register class for RegisterSDNode
2018-02-09 13:55:25 +00:00
r600cfg.ll
…
rcp-pattern.ll
…
read_register.ll
…
read-register-invalid-subtarget.ll
…
read-register-invalid-type-i32.ll
…
read-register-invalid-type-i64.ll
…
readcyclecounter.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
readlane_exec0.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
README
…
reduce-load-width-alignment.ll
…
reduce-saveexec.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
reduce-store-width-alignment.ll
…
reduction.ll
[AMDGPU] Support horizontal vectorization of min/max.
2018-05-09 21:18:34 +00:00
reg-coalescer-sched-crash.ll
…
regcoal-subrange-join.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
regcoalesce-dbg.mir
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
regcoalesce-prune.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
register-count-comments.ll
…
rename-disconnected-bug.ll
…
rename-independent-subregs-mac-operands.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
rename-independent-subregs.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
reorder-stores.ll
…
ret_jump.ll
[AMDGPU] fix tests to be independent of FP undef
2018-03-10 16:39:59 +00:00
ret.ll
Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
2018-02-27 16:59:10 +00:00
rewrite-out-arguments-address-space.ll
…
rewrite-out-arguments.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
rotl.i64.ll
…
rotl.ll
…
rotr.i64.ll
…
rotr.ll
…
rsq.ll
…
rv7x0_count3.ll
…
s_addk_i32.ll
…
s_movk_i32.ll
…
s_mulk_i32.ll
…
sad.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
saddo.ll
…
salu-to-valu.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
sampler-resource-id.ll
…
scalar_to_vector.ll
…
scalar-branch-missing-and-exec.ll
AMDGPU: Bring processors and features in sync with the spec
2018-02-16 21:26:25 +00:00
scalar-store-cache-flush.mir
[AMDGPU][Waitcnt] Update a few tests to use default waitcnt pass (si-insert-waitcnts) rather than old pass (si-insert-waits); this is a small step towards the overall goal of removing the old waitcnt pass, which is no longer maintained.
2018-04-27 17:59:15 +00:00
sched-crash-dbg-value.mir
[MIR] Add support for debug metadata for fixed stack objects
2018-04-25 18:58:06 +00:00
schedule-fs-loop-nested-if.ll
…
schedule-fs-loop-nested.ll
…
schedule-fs-loop.ll
…
schedule-global-loads.ll
…
schedule-if-2.ll
…
schedule-if.ll
…
schedule-ilp.ll
…
schedule-kernel-arg-loads.ll
…
schedule-regpressure-limit2.ll
…
schedule-regpressure-limit3.ll
[AMDGPU] Fix amdgpu-waves-per-eu accounting in scheduler
2018-05-12 01:41:56 +00:00
schedule-regpressure-limit.ll
…
schedule-regpressure.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
schedule-vs-if-nested-loop-failure.ll
…
schedule-vs-if-nested-loop.ll
…
scheduler-subrange-crash.ll
…
scratch-buffer.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
scratch-simple.ll
…
sdiv.ll
…
sdivrem24.ll
…
sdivrem64.ll
…
sdwa-gfx9.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
sdwa-peephole-instr.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
sdwa-peephole.ll
AMDGPU: Minor cleanups
2018-02-08 22:46:38 +00:00
sdwa-preserve.mir
[AMDGPU] Fix the SDWA Peephole phase to handle src for dst:UNUSED_PRESERVE.
2018-03-30 05:03:36 +00:00
sdwa-scalar-ops.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
sdwa-vop2-64bit.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
select64.ll
…
select-fabs-fneg-extract-legacy.ll
…
select-fabs-fneg-extract.ll
…
select-i1.ll
…
select-opt.ll
[AMDGPU] Fixed incorrect uniform branch condition
2018-01-09 21:34:43 +00:00
select-vectors.ll
…
select.f16.ll
…
select.ll
…
selectcc-cnd.ll
…
selectcc-cnde-int.ll
…
selectcc-icmp-select-float.ll
…
selectcc-opt.ll
…
selectcc.ll
…
selected-stack-object.ll
…
sendmsg-m0-hazard.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
set-dx10.ll
…
setcc64.ll
…
setcc-equivalent.ll
…
setcc-fneg-constant.ll
…
setcc-opt.ll
…
setcc-sext.ll
…
setcc.ll
[DAGCOmbine] Ensure that (brcond (setcc ...)) is handled in a canonical manner.
2018-02-23 11:50:42 +00:00
seto.ll
…
setuo.ll
…
sext-eliminate.ll
…
sext-in-reg-failure-r600.ll
…
sext-in-reg.ll
[AMDGPU] Enabled v2.16 literals for VOP3P
2018-04-17 23:09:05 +00:00
sgpr-control-flow.ll
…
sgpr-copy-duplicate-operand.ll
…
sgpr-copy.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
sgprcopies.ll
…
shared-op-cycle.ll
…
shift-and-i64-ubfe.ll
…
shift-and-i128-ubfe.ll
…
shift-i64-opts.ll
…
shl_add_constant.ll
…
shl_add_ptr.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
shl-add-to-add-shl.ll
…
shl.ll
…
shl.v2i16.ll
[AMDGPU] Enabled v2.16 literals for VOP3P
2018-04-17 23:09:05 +00:00
shrink-add-sub-constant.ll
…
shrink-carry.mir
[AMDGPU] Shrinking V_SUBBREV_U32
2018-02-24 01:32:32 +00:00
shrink-vop3-carry-out.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
si-annotate-cf-noloop.ll
…
si-annotate-cf-unreachable.ll
…
si-annotate-cf.ll
…
si-annotate-cfg-loop-assert.ll
…
si-fix-sgpr-copies.mir
AMDGPU: Don't leave dead illegal VGPR->SGPR copies
2018-03-19 14:07:15 +00:00
si-instr-info-correct-implicit-operands.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
si-lod-bias.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
si-lower-control-flow-kill.ll
AMDGPU: Remove deprecated llvm.AMDGPU.kilp intrinsic
2018-04-24 21:37:57 +00:00
si-lower-control-flow-unreachable-block.ll
…
si-scheduler.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
si-sgpr-spill.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
si-spill-cf.ll
…
si-spill-sgpr-stack.ll
…
si-triv-disjoint-mem-access.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
si-vector-hang.ll
…
sibling-call.ll
[AMDGPU] added writelane intrinsic
2018-02-28 19:10:32 +00:00
sign_extend.ll
…
simplify-libcalls.ll
…
simplifydemandedbits-recursion.ll
…
sint_to_fp.f64.ll
…
sint_to_fp.i64.ll
…
sint_to_fp.ll
…
sitofp.f16.ll
…
skip-if-dead.ll
[AMDGPU] fix test to be independent of FP undef
2018-03-09 16:33:34 +00:00
smed3.ll
…
sminmax.ll
…
sminmax.v2i16.ll
[AMDGPU] Enabled v2.16 literals for VOP3P
2018-04-17 23:09:05 +00:00
smrd-vccz-bug.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
smrd.ll
AMDGPU: Track physreg uses in SILoadStoreOptimizer
2018-02-23 10:45:56 +00:00
sopk-compares.ll
…
spill-alloc-sgpr-init-bug.ll
AMDGPU: Fix register name format in tests
2018-03-27 18:39:42 +00:00
spill-cfg-position.ll
…
spill-csr-frame-ptr-reg-copy.ll
AMDGPU: Move a flawed assert when spilling SGPRs
2018-04-23 16:13:30 +00:00
spill-empty-live-interval.mir
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
spill-m0.ll
[AMDGPU] Don't force WQM for DS op
2018-05-07 13:21:26 +00:00
spill-scavenge-offset.ll
…
spill-to-smem-m0.ll
…
spill-wide-sgpr.ll
…
split-scalar-i64-add.ll
…
split-smrd.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
split-vector-memoperand-offsets.ll
…
splitkit.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
sra.ll
…
srem.ll
…
srl.ll
…
ssubo.ll
…
stack-realign.ll
AMDGPU: Support realigning stack
2018-03-29 21:30:06 +00:00
stack-size-overflow.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
stack-slot-color-sgpr-vgpr-spills.mir
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
store_typed.ll
…
store-barrier.ll
…
store-global.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
store-hi16.ll
AMDGPU: Add D16 instructions preserve unused bits feature
2018-05-04 20:06:57 +00:00
store-local.ll
…
store-private.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
store-v3i64.ll
…
store-vector-ptrs.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
store-weird-sizes.ll
AMDGPU: Add combine for trunc of bitcast from build_vector
2018-05-09 18:37:39 +00:00
stress-calls.ll
…
structurize1.ll
…
structurize.ll
…
sub.i16.ll
…
sub.ll
…
sub.v2i16.ll
[AMDGPU] Use packed literals with zero either lower or hi part
2018-04-19 21:16:50 +00:00
subreg_interference.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
subreg-coalescer-crash.ll
…
subreg-coalescer-undef-use.ll
…
subreg-eliminate-dead.ll
…
subreg-intervals.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
swizzle-export.ll
…
syncscopes.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
tail-call-cgp.ll
…
target-cpu.ll
AMDGPU/SI: Extend promoting alloca to vector to arrays of up to 16 elements
2018-02-16 19:14:17 +00:00
tex-clause-antidep.ll
…
texture-input-merge.ll
…
trap.ll
…
trunc-bitcast-vector.ll
AMDGPU: Fix broken check lines in test
2018-05-08 18:43:44 +00:00
trunc-cmp-constant.ll
…
trunc-combine.ll
AMDGPU: Add combine for trunc of bitcast from build_vector
2018-05-09 18:37:39 +00:00
trunc-store-f64-to-f16.ll
…
trunc-store-i1.ll
…
trunc-store.ll
…
trunc-vector-store-assertion-failure.ll
…
trunc.ll
…
tti-unroll-prefs.ll
…
twoaddr-mad.mir
[MIR] Add support for debug metadata for fixed stack objects
2018-04-25 18:58:06 +00:00
uaddo.ll
…
udiv.ll
…
udivrem24.ll
…
udivrem64.ll
…
udivrem.ll
…
uint_to_fp.f64.ll
…
uint_to_fp.i64.ll
…
uint_to_fp.ll
…
uitofp.f16.ll
…
umed3.ll
…
unaligned-load-store.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
undefined-physreg-sgpr-spill.mir
[MIR] Add support for debug metadata for fixed stack objects
2018-04-25 18:58:06 +00:00
undefined-subreg-liverange.ll
…
unhandled-loop-condition-assertion.ll
…
uniform-branch-intrinsic-cond.ll
…
uniform-cfg.ll
[AMDGPU] Fixed incorrect uniform branch condition
2018-01-09 21:34:43 +00:00
uniform-crash.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
uniform-loop-inside-nonuniform.ll
[AMDGPU] Revert b0efc4fd6 (https://reviews.llvm.org/D40556)
2018-04-25 12:32:46 +00:00
unify-metadata.ll
…
unigine-liveness-crash.ll
[AMDGPU] fix tests to be independent of FP undef
2018-03-10 16:39:59 +00:00
unknown-processor.ll
…
unpack-half.ll
[SelectionDAG] Fixed f16-from-vector promotion problem
2018-01-09 21:36:25 +00:00
unroll.ll
…
unsupported-calls.ll
…
unsupported-cc.ll
…
urem.ll
…
use-sgpr-multiple-times.ll
…
usubo.ll
…
v1i64-kernel-arg.ll
…
v_cndmask.ll
…
v_cvt_pk_u8_f32.ll
…
v_mac_f16.ll
…
v_mac.ll
…
v_madak_f16.ll
…
valu-i1.ll
[AMDGPU] Revert b0efc4fd6 (https://reviews.llvm.org/D40556)
2018-04-25 12:32:46 +00:00
vccz-corrupt-bug-workaround.mir
[AMDGPU][Waitcnt] Remove the old waitcnt pass
2018-05-07 14:43:28 +00:00
vector-alloca-addrspacecast.ll
AMDGPU/SI: Don't promote alloca to vector for AddrSpaceCast instruction.
2018-05-11 22:17:57 +00:00
vector-alloca.ll
…
vector-extract-insert.ll
…
vectorize-global-local.ll
…
vertex-fetch-encoding.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
vgpr-spill-emergency-stack-slot-compute.ll
…
vgpr-spill-emergency-stack-slot.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
vi-removed-intrinsics.ll
…
vop-shrink-frame-index.mir
[MIR] Add support for debug metadata for fixed stack objects
2018-04-25 18:58:06 +00:00
vop-shrink-non-ssa.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
vop-shrink.ll
…
vselect64.ll
…
vselect.ll
…
vtx-fetch-branch.ll
…
vtx-schedule.ll
…
wait.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
waitcnt-back-edge-loop.mir
[AMDGPU] Do not only rely on BB number when finding bottom loop
2018-04-19 15:42:30 +00:00
waitcnt-debug.mir
[AMDGPU] Waitcnt pass: add debug options
2018-04-25 19:21:26 +00:00
waitcnt-flat.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
waitcnt-loop-single-basic-block.mir
[AMDGPU] Waitcnt pass: Modify the waitcnt pass to propagate info in the case of a single basic block loop. mergeInputScoreBrackets() does this for us; update it so that it processes the single bb's score bracket when processing the single bb's preds. It is, after all, a pred of itself, so it's score bracket is needed.
2018-03-14 22:04:32 +00:00
waitcnt-looptest.ll
[AMDGPU] Increased vector length for global/constant loads.
2018-03-07 17:09:18 +00:00
waitcnt-no-redundant.mir
[AMDGPU] Make note of existing waitcnt instrs; this is add-on work related to suppression of redundant waitcnt instrs. It is necessary to make note of these existing waitcnt instrs so that we do not fall into an infinite loop when handling loops. Also, [NFC] some minor code clean-up.
2018-02-19 19:19:59 +00:00
waitcnt-permute.mir
[AMDGPU][Waitcnt] Update a few tests to use default waitcnt pass (si-insert-waitcnts) rather than old pass (si-insert-waits); this is a small step towards the overall goal of removing the old waitcnt pass, which is no longer maintained.
2018-04-27 17:59:15 +00:00
waitcnt.mir
[AMDGPU][Waitcnt] Remove the old waitcnt pass
2018-05-07 14:43:28 +00:00
wave_dispatch_regs.ll
[AMDGPU] Ensure there are enough registers for wave dispatch
2018-04-11 17:18:36 +00:00
widen_extending_scalar_loads.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
widen-vselect-and-mask.ll
…
wqm.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
wqm.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
write_register.ll
…
write-register-vgpr-into-sgpr.ll
…
wrong-transalu-pos-fix.ll
…
xfail.r600.bitcast.ll
…
xnor.ll
AMDGPU: Add Vega12 and Vega20
2018-04-30 19:08:16 +00:00
xor.ll
…
zero_extend.ll
…
zext-i64-bit-operand.ll
…
zext-lid.ll
…

README 

+==============================================================================+
| How to organize the lit tests                                                |
+==============================================================================+

- If you write a test for matching a single DAG opcode or intrinsic, it should
  go in a file called {opcode_name,intrinsic_name}.ll (e.g. fadd.ll)

- If you write a test that matches several DAG opcodes and checks for a single
  ISA instruction, then that test should go in a file called {ISA_name}.ll (e.g.
  bfi_int.ll

- For all other tests, use your best judgement for organizing tests and naming
  the files.

+==============================================================================+
| Naming conventions                                                           |
+==============================================================================+

- Use dash '-' and not underscore '_' to separate words in file names, unless
  the file is named after a DAG opcode or ISA instruction that has an
  underscore '_' in its name.
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