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227 Commits

Author SHA1 Message Date
Hal Finkel 81e6fccbd7 Support little-endian encodings in the FixedLenDecoderEmitter 
The convention used to specify the PowerPC ISA is that bits are numbered in
reverse order (0 is the index of the high bit). To support this "little endian"
encoding convention, CodeEmitterGen will reverse the bit numberings prior to
generating the encoding tables. In order to generate a disassembler,
FixedLenDecoderEmitter needs to do the same.

This moves the bit reversal logic out of CodeEmitterGen and into CodeGenTarget
(where it can be used by both CodeEmitterGen and FixedLenDecoderEmitter). This
is prep work for disassembly support in the PPC backend (which is the only
in-tree user of this little-endian encoding support).

llvm-svn: 197532
 2013-12-17 22:37:50 +00:00
Andrew Trick 74f4c749cf Lower stackmap intrinsics directly to their target opcode in the DAG builder. 
llvm-svn: 193769
 2013-10-31 17:18:24 +00:00
Pete Cooper d54381749d Add v4f16 to supported value types. 
This is useful for some ARM intrinsics such as VCVTN which does a <4 x float> <-> <4 x half> conversion.

llvm-svn: 191870
 2013-10-03 03:29:21 +00:00
Jiangning Liu 63dc840fc5 Initial support for Neon scalar instructions. 
Patch by Ana Pazos.

1.Added support for v1ix and v1fx types.
2.Added Scalar Pairwise Reduce instructions.
3.Added initial implementation of Scalar Arithmetic instructions.

llvm-svn: 191263
 2013-09-24 02:47:27 +00:00
Jack Carter 52f2bea0d3 [Mips][msa] Value types for MSA support. 
Added v8f16 to ValueTypes.h, ValueTypes.cpp, ValueTypes.td, 
and CodeGenTarget.cpp

Patch by Daniel Sanders

llvm-svn: 188326
 2013-08-13 22:34:26 +00:00
Craig Topper 06b3b6651e Add 'const' qualifier to some arrays. 
llvm-svn: 186312
 2013-07-15 08:02:13 +00:00
Nick Lewycky c2ec0725ce Extend 'readonly' and 'readnone' to work on function arguments as well as 
functions. Make the function attributes pass add it to known library functions
and when it can deduce it.

llvm-svn: 185735
 2013-07-06 00:29:58 +00:00
Jakob Stoklund Olesen 13d4a07fa9 Use ArrayRef<MVT::SimpleValueType> when possible. 
Not passing vector references around makes it possible to use
SmallVector in most places.

llvm-svn: 177235
 2013-03-17 17:26:09 +00:00
Elena Demikhovsky 517afbff01 Added 6 more value types: v32i1, v64i1, v32i16, v32i8, v64i8, v8f64 
llvm-svn: 171026
 2012-12-24 10:03:57 +00:00
Chandler Carruth 91d19d8e93 Sort the #include lines for utils/... 
I've tried to find main moudle headers where possible, but the TableGen
stuff may warrant someone else looking at it.

llvm-svn: 169251
 2012-12-04 10:37:14 +00:00
Joerg Sonnenberger 635debe85b Remove exception handling usage from tblgen. 
Most places can use PrintFatalError as the unwinding mechanism was not
used for anything other than printing the error. The single exception
was CodeGenDAGPatterns.cpp, where intermediate errors during type
resolution were ignored to simplify incremental platform development.
This use is replaced by an error flag in TreePattern and bailout earlier
in various places if it is set. 

llvm-svn: 166712
 2012-10-25 20:33:17 +00:00
Micah Villmow 75e29c4b78 Add in new data types that are used by AMDIL/ANL among others. 
llvm-svn: 164261
 2012-09-19 22:47:07 +00:00
Owen Anderson ccd682c695 Compute a map from register names to registers, rather than scanning the list of registers every time we want to look up a register by name. 
llvm-svn: 163659
 2012-09-11 23:32:17 +00:00
Nadav Rotem 7c277da364 Add a new optimization pass: Stack Coloring, that merges disjoint static allocations (allocas). Allocas are known to be 
disjoint if they are marked by disjoint lifetime markers (@llvm.lifetime.XXX intrinsics).

llvm-svn: 163299
 2012-09-06 09:17:37 +00:00
Jakob Stoklund Olesen 9dc03bba14 Add CodeGenTarget::guessInstructionProperties. 
Currently, TableGen just guesses instruction properties when it can't
infer them form patterns.

This adds a guessInstructionProperties flag to the instruction set
definition that will be used to disable guessing. The flag is intended
as a migration aid. It will be removed again when no more targets need
their properties guessed.

llvm-svn: 162460
 2012-08-23 19:34:41 +00:00
Andrew Trick 87255e340e I'm introducing a new machine model to simultaneously allow simple 
subtarget CPU descriptions and support new features of
MachineScheduler.

MachineModel has three categories of data:
1) Basic properties for coarse grained instruction cost model.
2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD).
3) Instruction itineraties for detailed per-cycle reservation tables.

These will all live side-by-side. Any subtarget can use any
combination of them. Instruction itineraries will not change in the
near term. In the long run, I expect them to only be relevant for
in-order VLIW machines that have complex contraints and require a
precise scheduling/bundling model. Once itineraries are only actively
used by VLIW-ish targets, they could be replaced by something more
appropriate for those targets.

This tablegen backend rewrite sets things up for introducing
MachineModel type #2: per opcode/operand cost model.

llvm-svn: 159891
 2012-07-07 04:00:00 +00:00
Andrew Trick 91118a6155 whitespace 
llvm-svn: 159890
 2012-07-07 03:59:51 +00:00
Chris Lattner ff9e08baf9 rdar://11542750 - llvm.trap should be marked no return. 
llvm-svn: 157551
 2012-05-27 23:20:41 +00:00
Jim Grosbach 53733cdb23 Revert "Emit the SubRegTable with the smallest possible integer type." 
This reverts commit 151760.

We want to move getSubReg() from TargetRegisterInfo into MCRegisterInfo,
but to do that, the type of the lookup table needs to be the same for
all targets.

llvm-svn: 151814
 2012-03-01 17:30:35 +00:00
Benjamin Kramer c80c3fd5a7 Emit the SubRegTable with the smallest possible integer type. 
Doesn't help ARM with its massive register set, but halves the size on x86 and all other targets.

llvm-svn: 151760
 2012-02-29 21:57:08 +00:00
Craig Topper c4965bce14 Convert assert(0) to llvm_unreachable 
llvm-svn: 149814
 2012-02-05 07:21:30 +00:00
Pete Cooper 9bcb72136e Added MVT::v2f16 
llvm-svn: 148067
 2012-01-12 23:14:13 +00:00
Devang Patel 85d684a4d9 Split AsmParser into two components - AsmParser and AsmParserVariant 
AsmParser holds info specific to target parser.
AsmParserVariant holds info specific to asm variants supported by the target.

llvm-svn: 147787
 2012-01-09 19:13:28 +00:00
Dan Gohman 94580ab375 Add basic generic CodeGen support for half. 
llvm-svn: 146927
 2011-12-20 00:02:33 +00:00
Evan Cheng 2a81dd4a3c First chunk of MachineInstr bundle support. 
1. Added opcode BUNDLE
2. Taught MachineInstr class to deal with bundled MIs
3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs
4. Taught MachineBasicBlock methods about bundled MIs

llvm-svn: 145975
 2011-12-06 22:12:01 +00:00