Commit Graph

232 Commits

Author SHA1 Message Date
Quentin Colombet 1fb3362a6e [RegAlloc] Make tryInstructionSplit less aggressive.
The greedy register allocator tries to split a live-range around each
instruction where it is used or defined to relax the constraints on the entire
live-range (this is a last chance split before falling back to spill).
The goal is to have a big live-range that is unconstrained (i.e., that can use
the largest legal register class) and several small local live-range that carry
the constraints implied by each instruction.
E.g.,
Let csti be the constraints on operation i.

V1=
op1 V1(cst1)
op2 V1(cst2)

V1 live-range is constrained on the intersection of cst1 and cst2.

tryInstructionSplit relaxes those constraints by aggressively splitting each
def/use point:
V1=
V2 = V1
V3 = V2
op1 V3(cst1)
V4 = V2
op2 V4(cst2)

Because of how the coalescer infrastructure works, each new variable (V3, V4)
that is alive at the same time as V1 (or its copy, here V2) interfere with V1.
Thus, we end up with an uncoalescable copy for each split point.

To make tryInstructionSplit less aggressive, we check if the split point
actually relaxes the constraints on the whole live-range. If it does not, we do
not insert it.
Indeed, it will not help the global allocation problem:
- V1 will have the same constraints.
- V1 will have the same interference + possibly the newly added split variable
  VS.
- VS will produce an uncoalesceable copy if alive at the same time as V1.

<rdar://problem/15570057>

llvm-svn: 198369
2014-01-02 22:47:22 +00:00
Michael Gottesman 5e985ee5b5 [block-freq] Rename getEntryFrequency() -> getEntryFreq() to match getBlockFreq() in all *BlockFrequencyInfo*.
llvm-svn: 197304
2013-12-14 02:37:38 +00:00
Michael Gottesman b78dec8faf [block-freq] Update MachineBlockPlacement and RegAllocGreedy to use the new MachineBlockFrequencyInfo methods.
llvm-svn: 197290
2013-12-14 00:25:45 +00:00
Andrew Trick 2d8826a1b5 Add TargetRegisterInfo::reverseLocalAssignment hook.
This hook reverses the order of assignment for local live ranges. This
will generally allocate shorter local live ranges first. For targets with
many registers, this could reduce regalloc compile time by a large
factor. It should still achieve optimal coloring; however, it can change
register eviction decisions. It is disabled by default for two reasons:
(1) Top-down allocation is simpler and easier to debug for targets that
don't benefit from reversing the order.
(2) Bottom-up allocation could result in poor evicition decisions on some
targets affecting the performance of compiled code.

llvm-svn: 197001
2013-12-11 03:40:15 +00:00
Aditya Nandakumar 73f3d33dbb Check hint registers for interference only once before evictions
llvm-svn: 196536
2013-12-05 21:18:40 +00:00
Andrew Trick c2ab53a318 Reverse the order of eviction checks for possible compile time savings. No functionality.
llvm-svn: 195969
2013-11-29 23:49:38 +00:00
Andrew Trick 059e800fda DEBUG shouldEvict decisions
llvm-svn: 195490
2013-11-22 19:07:42 +00:00
Andrew Trick 3621b8a217 Minor cleanup. EvictionCost ctor was confusing relative to the other costs floating around in the code.
llvm-svn: 195489
2013-11-22 19:07:38 +00:00
Aditya Nandakumar c1fd0dd419 Fixed an extra for(typo) in the comments
llvm-svn: 195171
2013-11-19 23:51:32 +00:00
Aaron Ballman 04999041e8 Replacing HUGE_VALF with llvm::huge_valf in order to work around a warning triggered in MSVC 12.
Patch reviewed by Reid Kleckner and Jim Grosbach.

llvm-svn: 194533
2013-11-13 00:15:44 +00:00
Arnaud A. de Grandmaison ea3ac1612c CalcSpillWeights: give a better describing name to calculateSpillWeights
Besides, this relates it more obviously to the VirtRegAuxInfo::calculateSpillWeightAndHint.

No functionnal change.

llvm-svn: 194404
2013-11-11 19:04:45 +00:00
Arnaud A. de Grandmaison 760c1e0b0a CalculateSpillWeights does not need to be a pass
Based on discussions with Lang Hames and Jakob Stoklund Olesen at the hacker's lab, and in the light of upcoming work on the PBQP register allocator, it was though that CalcSpillWeights does not need to be a pass. This change will enable to customize / tune the spill weight computation depending on the allocator.

Update the documentation style while there.

No functionnal change.

llvm-svn: 194356
2013-11-10 17:46:31 +00:00
Arnaud A. de Grandmaison f7a60a8e01 Revert "CalculateSpillWeights does not need to be a pass"
Temporarily revert my previous commit until I understand why it breaks 3 target tests.

llvm-svn: 194272
2013-11-08 18:19:19 +00:00
Arnaud A. de Grandmaison ed812f6590 CalculateSpillWeights does not need to be a pass
Based on discussions with Lang Hames and Jakob Stoklund Olesen at the hacker's lab, and in the light of upcoming work on the PBQP register allocator, it was though that CalcSpillWeights does not need to be a pass. This change will enable to customize / tune the spill weight computation depending on the allocator.

Update the documentation style while there.

No functionnal change.

llvm-svn: 194269
2013-11-08 17:56:29 +00:00
Matthias Braun 34e1be9451 Represent RegUnit liveness with LiveRange instance
Previously LiveInterval has been used, but having a spill weight and
register number is unnecessary for a register unit.

llvm-svn: 192397
2013-10-10 21:29:02 +00:00
Reid Kleckner cd4a25d66e Explicitly request unsigned enum types when desired
This fixes repeated -Wmicrosoft warnings when self-hosting clang on
Windows, and gets us real unsigned enum types with MSVC.

llvm-svn: 192227
2013-10-08 20:15:11 +00:00
Eli Friedman 78bffa5767 Fix unused variables.
llvm-svn: 190448
2013-09-10 23:18:14 +00:00
Mark Lacey f9ea88546f Track new virtual registers by register number.
Track new virtual registers by register number, rather than by the live
interval created for them. This is the first step in separating the
creation of new virtual registers and new live intervals.  Eventually
live intervals will be created and populated on demand after the virtual
registers have been created and used in instructions.

llvm-svn: 188434
2013-08-14 23:50:04 +00:00
Andrew Trick c7934b3e37 Down-scale slot index distance to save bits.
llvm-svn: 187438
2013-07-30 19:59:19 +00:00
Andrew Trick f4b1ee3492 RegAllocGreedy comment.
llvm-svn: 187141
2013-07-25 18:35:22 +00:00
Andrew Trick 8bb0a251fd Evict local live ranges if they can be reassigned.
The previous change to local live range allocation also suppressed
eviction of local ranges. In rare cases, this could result in more
expensive register choices. This commit actually revives a feature
that I added long ago: check if live ranges can be reassigned before
eviction. But now it only happens in rare cases of evicting a local
live range because another local live range wants a cheaper register.

The benefit is improved code size for some benchmarks on x86 and armv7.

I measured no significant compile time increase and performance
changes are noise.

llvm-svn: 187140
2013-07-25 18:35:19 +00:00
Andrew Trick 8485257d6d Allocate local registers in order for optimal coloring.
Also avoid locals evicting locals just because they want a cheaper register.

Problem: MI Sched knows exactly how many registers we have and assumes
they can be colored. In cases where we have large blocks, usually from
unrolled loops, greedy coloring fails. This is a source of
"regressions" from the MI Scheduler on x86. I noticed this issue on
x86 where we have long chains of two-address defs in the same live
range. It's easy to see this in matrix multiplication benchmarks like
IRSmk and even the unit test misched-matmul.ll.

A fundamental difference between the LLVM register allocator and
conventional graph coloring is that in our model a live range can't
discover its neighbors, it can only verify its neighbors. That's why
we initially went for greedy coloring and added eviction to deal with
the hard cases. However, for singly defined and two-address live
ranges, we can optimally color without visiting neighbors simply by
processing the live ranges in instruction order.

Other beneficial side effects:

It is much easier to understand and debug regalloc for large blocks
when the live ranges are allocated in order. Yes, global allocation is
still very confusing, but it's nice to be able to comprehend what
happened locally.

Heuristics could be added to bias register assignment based on
instruction locality (think late register pairing, banks...).

Intuituvely this will make some test cases that are on the threshold
of register pressure more stable.

llvm-svn: 187139
2013-07-25 18:35:14 +00:00
Andrew Trick 9706496b0d Dump LIS before regalloc. MI sched changes them.
llvm-svn: 187107
2013-07-25 07:26:26 +00:00
Jakob Stoklund Olesen efeb3a1969 Remove floats from live range splitting costs.
These floats all represented block frequencies anyway, so just use the
BlockFrequency class directly.

Some floating point computations remain in tryLocalSplit(). They are
estimating spill weights which are still floats.

llvm-svn: 186435
2013-07-16 18:26:18 +00:00
Benjamin Kramer e2a1d89e14 Switch spill weights from a basic loop depth estimation to BlockFrequencyInfo.
The main advantages here are way better heuristics, taking into account not
just loop depth but also __builtin_expect and other static heuristics and will
eventually learn how to use profile info. Most of the work in this patch is
pushing the MachineBlockFrequencyInfo analysis into the right places.

This is good for a 5% speedup on zlib's deflate (x86_64), there were some very
unfortunate spilling decisions in its hottest loop in longest_match(). Other
benchmarks I tried were mostly neutral.

This changes register allocation in subtle ways, update the tests for it.
2012-02-20-MachineCPBug.ll was deleted as it's very fragile and the instruction
it looked for was gone already (but the FileCheck pattern picked up unrelated
stuff).

llvm-svn: 184105
2013-06-17 19:00:36 +00:00