Commit Graph

1203 Commits

Author SHA1 Message Date
Evandro Menezes 04abc14fb5 [AArch64] Change the preferred alignment for char and short to word alignment
Differential Revision: http://reviews.llvm.org/D21414

llvm-svn: 273280
2016-06-21 15:55:29 +00:00
Jan Vesely 9674bd4f97 NVPTX: Add supported CL features
Fixes libclc compilation broken by r269670

Reviewers: jholewinsky

Differential Revision: http://reviews.llvm.org/D20389

llvm-svn: 273031
2016-06-17 19:02:14 +00:00
Jan Vesely 211ba785d9 AMDGPU: Fix supported CL features
Reviewers: arsenm

Differential Revision: http://reviews.llvm.org/D20388

llvm-svn: 272986
2016-06-17 02:25:03 +00:00
Chris Dewhurst fe9e509b0c [Sparc] setjmp and longjmp intrinsic support update to add unit tests and remove accidentally checked-in code.
Related to revision r272782

llvm-svn: 272798
2016-06-15 16:08:13 +00:00
Chris Dewhurst 0381cd7dbf [Sparc] Change to let clang know that setjmp and longjmp intrinsics are implemented in the back-end.
Differential Revision: http://reviews.llvm.org/D19798

llvm-svn: 272782
2016-06-15 12:44:47 +00:00
Daniel Sanders 32b2d6b160 [mips] Defer validity check for CPU/ABI pairs and improve error message for invalid cases.
Summary:
The validity of ABI/CPU pairs is no longer checked on the fly but is
instead checked after initialization. As a result, invalid CPU/ABI pairs
can be reported as being known but invalid instead of being unknown. For
example, we now emit:
  error: ABI 'n32' is not supported on CPU 'mips32r2'
instead of:
  error: unknown target ABI 'n64'

Reviewers: atanasyan

Subscribers: sdardis, cfe-commits

Differential Revision: http://reviews.llvm.org/D21023

llvm-svn: 272645
2016-06-14 08:58:50 +00:00
Matt Arsenault 250024f905 AMDGPU: Verify subtarget specific builtins
Cleanup setup of subtarget features.

llvm-svn: 272091
2016-06-08 01:56:42 +00:00
Daniel Sanders 28d8637e25 [mips] The P5600 does not support N32/N64 since it's a 32-bit CPU.
Summary:

Reviewers: atanasyan

Subscribers: cfe-commits, sdardis

Differential Revision: http://reviews.llvm.org/D20963

llvm-svn: 271877
2016-06-06 09:47:32 +00:00
Daniel Sanders 26a56adaea [mips] Replace almost all Arch checks in MipsTargetInfo with ABI checks. NFC.
Summary:
setABI() is still tied to the Arch component of the Triple to preserve existing
behaviour.

Reviewers: atanasyan

Subscribers: cfe-commits

Differential Revision: http://reviews.llvm.org/D20961

llvm-svn: 271875
2016-06-06 09:07:08 +00:00
Daniel Sanders 55e4069702 [mips] Slightly simplify MipsTargetInfo::setDataLayout(). NFC.
Summary:

Reviewers: atanasyan

Subscribers: atanasyan, cfe-commits

Differential Revision: http://reviews.llvm.org/D20680

llvm-svn: 271647
2016-06-03 10:11:01 +00:00
Sjoerd Meijer 90df4a7c31 This adds target support and tests for Cortex-A73
Differential Revision: http://reviews.llvm.org/D20864

llvm-svn: 271507
2016-06-02 10:48:37 +00:00
Matt Arsenault 6dc455fb93 AMDGPU: Update datalayout string
llvm-svn: 271297
2016-05-31 16:58:18 +00:00
Daniel Sanders 07c8654284 [mips] Kill 'support' for untested EABI.
Summary:
There are no llvm backend tests* for EABI and no EABI buildbots. There were only
three clang tests, all of which checked that -mabi=eabi was passed to the
assembler.

*There is a single backend test that specifies EABI but it actually tests MIPS16.

Reviewers: atanasyan

Subscribers: emaste, sdardis, atanasyan, cfe-commits

Differential Revision: http://reviews.llvm.org/D20679

llvm-svn: 270998
2016-05-27 14:30:23 +00:00
Daniel Sanders 4672af6fec [mips] Fold MipsTargetInfoBase subclasses into MipsTargetInfoBase and rename to MipsTargetInfo. NFC
Summary:
This unifies mips/mipsel and mips64/mips64el into a single class so that we can
later support O32 on mips64/mips64el and N32/N64 on mips/mipsel (when an
appropriate CPU selected).

Reviewers: atanasyan

Subscribers: atanasyan, jfb, cfe-commits, dschuff

Differential Revision: http://reviews.llvm.org/D20678

llvm-svn: 270984
2016-05-27 11:51:02 +00:00
Renato Golin 3b8709c583 Revert "[AArch64] Using new TargetParser in Clang"
This reverts commit r270688 and r270689. The issue is not a random order, but a
different order for some targets and others (prob. Linux vs Darwin). Reverting until
we have a better fix.

llvm-svn: 270691
2016-05-25 12:36:31 +00:00
Renato Golin d4d4da74a6 [AArch64] Using new TargetParser in Clang
Using AArch64TargetParser in clang to avoid repetitive string parsing.

Use TargetParser to do ARCH/CPU/ArchExt parsing instead of local implementation.

Patch by Jojo Ma.

llvm-svn: 270688
2016-05-25 12:02:58 +00:00
Jacob Baungard Hansen 13a4937404 [Sparc] Add software float option -msoft-float
Summary:
Following patch D19265 which enable software floating point support in the Sparc backend, this patch enables the option to be enabled in the front-end using the -msoft-float option.

The user should ensure a library (such as the builtins from Compiler-RT) that includes the software floating point routines is provided.

Reviewers: jyknight, lero_chris

Subscribers: jyknight, cfe-commits

Differential Revision: http://reviews.llvm.org/D20419

llvm-svn: 270538
2016-05-24 08:30:08 +00:00
Dimitry Andric c6d924cd06 Make __FreeBSD_cc_version predefined macro configurable at build time
The `FreeBSDTargetInfo` class has always set the `__FreeBSD_cc_version`
predefined macro to a rather static value, calculated from the major OS
version.

In the FreeBSD base system, we will start incrementing the value of this
macro whenever we make any signifant change to clang, so we need a way
to configure the macro's value at build time.

Use `FREEBSD_CC_VERSION` for this, which we can define in the FreeBSD
build system using either the `-D` command line option, or an include
file.  Stock builds will keep the earlier value.

Differential Revision: http://reviews.llvm.org/D20037

llvm-svn: 270240
2016-05-20 17:27:22 +00:00
Benjamin Kramer f4c520d5d2 Add all the avx512 flavors to __builtin_cpu_supports's list.
This is matching what trunk gcc is accepting. Also adds a missing ssse3
case. PR27779. The amount of duplication here is annoying, maybe it
should be factored into a separate .def file?

llvm-svn: 270224
2016-05-20 15:21:08 +00:00
Krzysztof Parzyszek 89fb44147b [Hexagon] Recognize "s" constraint in inline-asm
llvm-svn: 270216
2016-05-20 13:50:32 +00:00
Artem Belevich ffa5fc51b8 [CUDA] Allow sm_50,52,53 GPUs
LLVM accepts them since r233575.

Differential Revision: http://reviews.llvm.org/D20405

llvm-svn: 270084
2016-05-19 17:47:47 +00:00
Krzysztof Parzyszek e0026e4e21 [Hexagon] Recognize "q" and "v" in inline-asm as register constraints
Clang follow-up to r269933.

llvm-svn: 269934
2016-05-18 14:56:14 +00:00
Ashutosh Nema 51c9dd0081 Add new intrinsic support for MONITORX and MWAITX instructions
Summary:
MONITORX/MWAITX instructions provide similar capability to the MONITOR/MWAIT
pair while adding a timer function, such that another termination of the MWAITX
instruction occurs when the timer expires. The presence of the MONITORX and 
MWAITX instructions is indicated by CPUID 8000_0001, ECX, bit 29.

The MONITORX and MWAITX instructions are intercepted by the same bits that
intercept MONITOR and MWAIT. MONITORX instruction establishes a range to be
monitored. MWAITX instruction causes the processor to stop instruction
execution and enter an implementation-dependent optimized state until
occurrence of a class of events.

Opcode of MONITORX instruction is "0F 01 FA". Opcode of MWAITX instruction is
"0F 01 FB". These opcode information is used in adding tests for the
disassembler.

These instructions are enabled for AMD's bdver4 architecture.

Patch by Ganesh Gopalasubramanian!

Reviewers: echristo, craig.topper

Subscribers: RKSimon, joker.eph, llvm-commits, cfe-commits

Differential Revision: http://reviews.llvm.org/D19796

llvm-svn: 269907
2016-05-18 11:56:23 +00:00
Paul Robinson 9d61361acb [PS4] Change the names of some "environmental" things to what our
licensees actually see in the toolchain we deliver to them.  This will
reduce the set of local patches we have to maintain.  The triple is
not changing.  (The term ORBIS is an internal code name for PS4.)

llvm-svn: 269671
2016-05-16 17:22:25 +00:00
Yaxun Liu 39cf40f6b4 [OpenCL] Add supported OpenCL extensions to target info.
Add supported OpenCL extensions to target info. It serves as default values to save the users of the burden setting each supported extensions and optional core features in command line.

Re-commit after fixing build error due to missing override attribute.

Differential Revision: http://reviews.llvm.org/D19484

llvm-svn: 269670
2016-05-16 17:06:34 +00:00