Commit Graph

1215 Commits

Author SHA1 Message Date
Erich Keane 46441fdb3c Implement P1771
As passed in the Cologne meeting and treated by Core as a DR,
[[nodiscard]] was applied to constructors so that they can be diagnosed
in cases where the user forgets a variable name for a type.

The intent is to enable the library to start using this on the
constructors of scope_guard/lock_guard.

Differential Revision: https://reviews.llvm.org/D64914

llvm-svn: 367027
2019-07-25 15:10:56 +00:00
Anastasia Stulova 88ed70e247 [OpenCL] Rename lang mode flag for C++ mode
Rename lang mode flag to -cl-std=clc++/-cl-std=CLC++
or -std=clc++/-std=CLC++.

This aligns with OpenCL C conversion and removes ambiguity
with OpenCL C++. 

Differential Revision: https://reviews.llvm.org/D65102

llvm-svn: 367008
2019-07-25 11:04:29 +00:00
Rainer Orth 2da6eea07c [clang, test] Fix Clang :: Headers/max_align.c on 64-bit SPARC
Clang :: Headers/max_align.c currently FAILs on 64-bit SPARC:

  error: 'error' diagnostics seen but not expected: 
    File /vol/llvm/src/clang/dist/test/Headers/max_align.c Line 12: static_assert failed due to requirement '8 == _Alignof(max_align_t)' ""
  1 error generated.

This happens because SuitableAlign isn't defined for SPARCv9 unlike SPARCv8
(which uses the default of 64 bits).  gcc's sparc/sparc.h has

  #define BIGGEST_ALIGNMENT (TARGET_ARCH64 ? 128 : 64)

This patch sets SuitableAlign to match and updates the corresponding testcase.

Tested on sparcv9-sun-solaris2.11.

Differential Revision: https://reviews.llvm.org/D64487

llvm-svn: 366820
2019-07-23 16:24:00 +00:00
Aaron Ballman 1f5712ebb5 Revert the change to the [[nodiscard]] feature test macro value.
This value only gets bumped once both P1301 and P1771 are implemented.

llvm-svn: 366682
2019-07-22 12:49:28 +00:00
Aaron Ballman 3bef014e7d Implement P1301R4, which allows specifying an optional message on the [[nodiscard]] attribute.
This also bumps the attribute feature test value and introduces the notion of a C++2a extension warning.

llvm-svn: 366626
2019-07-20 07:56:34 +00:00
Alex Bradbury e078967adf [RISCV] Hard float ABI support
The RISC-V hard float calling convention requires the frontend to:

* Detect cases where, once "flattened", a struct can be passed using
int+fp or fp+fp registers under the hard float ABI and coerce to the
appropriate type(s)
* Track usage of GPRs and FPRs in order to gate the above, and to
determine when signext/zeroext attributes must be added to integer
scalars

This patch attempts to do this in compliance with the documented ABI,
and uses ABIArgInfo::CoerceAndExpand in order to do this. @rjmccall, as
author of that code I've tagged you as reviewer for initial feedback on
my usage.

Note that a previous version of the ABI indicated that when passing an
int+fp struct using a GPR+FPR, the int would need to be sign or
zero-extended appropriately. GCC never did this and the ABI was changed,
which makes life easier as ABIArgInfo::CoerceAndExpand can't currently
handle sign/zero-extension attributes.

Re-landed after backing out 366450 due to missed hunks.

Differential Revision: https://reviews.llvm.org/D60456

llvm-svn: 366480
2019-07-18 18:29:59 +00:00
Alex Bradbury 9b732fe99b Revert "[RISCV] Hard float ABI support" r366450
The commit was missing a few hunks. Will fix and recommit.

llvm-svn: 366454
2019-07-18 16:13:17 +00:00
Alex Bradbury fc3aa2ab48 [RISCV] Hard float ABI support
The RISC-V hard float calling convention requires the frontend to:

* Detect cases where, once "flattened", a struct can be passed using
int+fp or fp+fp registers under the hard float ABI and coerce to the
appropriate type(s) * Track usage of GPRs and FPRs in order to gate the
above, and to
determine when signext/zeroext attributes must be added to integer
scalars

This patch attempts to do this in compliance with the documented ABI,
and uses ABIArgInfo::CoerceAndExpand in order to do this. @rjmccall, as
author of that code I've tagged you as reviewer for initial feedback on
my usage.

Note that a previous version of the ABI indicated that when passing an
int+fp struct using a GPR+FPR, the int would need to be sign or
zero-extended appropriately. GCC never did this and the ABI was changed,
which makes life easier as ABIArgInfo::CoerceAndExpand can't currently
handle sign/zero-extension attributes.

Differential Revision: https://reviews.llvm.org/D60456

llvm-svn: 366450
2019-07-18 15:33:41 +00:00
Nathan Lanza 49e14cefbe Change a lit test to permit vendor specific clang version
A test manually checks for the string `__VERSION__ "Clang`. This needs
to permit vendor specific variants.

llvm-svn: 366166
2019-07-16 02:05:52 +00:00
Nathan Lanza 50f0c82453 Allow for vendor prefixes in a list test
Summary:
Preprocessor/init.c contains a line that explicitly checks for the
string

__VERSION__ "Clang{{.*}}

It's valid to have a toolchain configured to emit a vendor prefix
before the word Clang. e.g.

__VERSION__ "Vendor Clang{{.*}}

Subscribers: fedor.sergeev, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D64772

llvm-svn: 366159
2019-07-16 00:57:50 +00:00
Sylvestre Ledru 56799837a4 Update __VERSION__ to remove the hardcoded 4.2.1 version
Summary:
Just like in https://reviews.llvm.org/D56803
for -dumpversion

Reviewers: rnk

Reviewed By: rnk

Subscribers: dexonsmith, lebedev.ri, hubert.reinterpretcast, xbolva00, fedor.sergeev, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D63048

llvm-svn: 366091
2019-07-15 17:47:22 +00:00
Alexandros Lamprineas 951bb68ce2 [TargetParser][ARM] Account dependencies when processing target features
Teaches ARM::appendArchExtFeatures to account dependencies when processing
target features: i.e. when you say -march=armv8.1-m.main+mve.fp+nofp it
means mve.fp should get discarded too. (Split from D63936)

Differential Revision: https://reviews.llvm.org/D64048

llvm-svn: 366031
2019-07-14 20:31:15 +00:00
JF Bastien fff5dc0b17 Support __seg_fs and __seg_gs on x86
Summary:
GCC supports named address spaces macros:
  https://gcc.gnu.org/onlinedocs/gcc/Named-Address-Spaces.html

clang does as well with address spaces:
  https://clang.llvm.org/docs/LanguageExtensions.html#memory-references-to-specified-segments

Add the __seg_fs and __seg_gs macros for compatibility with GCC.

<rdar://problem/52944935>

Subscribers: jkorous, dexonsmith, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D64676

llvm-svn: 366028
2019-07-14 18:33:51 +00:00
Sylvestre Ledru 21a92a8a55 This reverts commit 632a36bfcfc8273c1861f04ff6758d863c47c784.
Some targets such as Python 2.7.16 still use VERSION in
their builds. Without VERSION defined, the source code
has syntax errors.

Reverting as it will probably break many other things.

Noticed by Sterling Augustine

llvm-svn: 365992
2019-07-13 06:27:35 +00:00
Sylvestre Ledru 603580216f Remove __VERSION__
Summary:
It has been introduced in 2011 for gcc compat:
https://github.com/llvm-mirror/clang/commit/ad1a4c6e89594e704775ddb6b036ac982fd68cad
it is probably time to remove it


Reviewers: rnk, dexonsmith

Reviewed By: rnk

Subscribers: dschuff, aheejin, fedor.sergeev, arphaman, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D64062

llvm-svn: 365962
2019-07-12 21:45:08 +00:00
Ulrich Weigand b98bf60ef7 [SystemZ] Add support for new cpu architecture - arch13
This patch series adds support for the next-generation arch13
CPU architecture to the SystemZ backend.

This includes:
- Basic support for the new processor and its features.
- Support for low-level builtins mapped to new LLVM intrinsics.
- New high-level intrinsics in vecintrin.h.
- Indicate support by defining  __VEC__ == 10303.

Note: No currently available Z system supports the arch13
architecture.  Once new systems become available, the
official system name will be added as supported -march name.

llvm-svn: 365933
2019-07-12 18:14:51 +00:00
Reid Kleckner fa52674ac0 Fix has_attribute.cpp test on Windows after r364102
llvm-svn: 364108
2019-06-21 22:28:52 +00:00
Richard Smith 5050a8da18 Fix __has_cpp_attribute expansion to produce trailing L and (where
necessary) leading whitespace.

Simplify unit test and extend to cover no_unique_address attribute.

llvm-svn: 364102
2019-06-21 20:20:21 +00:00
Aaron Puchert 2b285c664d Fix tests after r363749
We changed -Wmissing-prototypes there, which was used in these tests via
-Weverything.

llvm-svn: 363754
2019-06-18 23:40:17 +00:00
Rainer Orth abccb1ad89 Clang :: Sema/wchar.c has long been failing on Solaris:
error: 'error' diagnostics expected but not seen: 
    File /vol/llvm/src/clang/local/test/Sema/wchar.c Line 22: initializing wide char array with non-wide string literal
  error: 'error' diagnostics seen but not expected: 
    File /vol/llvm/src/clang/local/test/Sema/wchar.c Line 20: array initializer must be an initializer list
    File /vol/llvm/src/clang/local/test/Sema/wchar.c Line 22: array initializer must be an initializer list

It turns out the definition is wrong, as can be seen in GCC's gcc/config/sol2.h:

  /* wchar_t is called differently in <wchar.h> for 32 and 64-bit
     compilations.  This is called for by SCD 2.4.1, p. 6-83, Figure 6-65
     (32-bit) and p. 6P-10, Figure 6.38 (64-bit).  */
  
  #undef WCHAR_TYPE
  #define WCHAR_TYPE (TARGET_64BIT ? "int" : "long int")

The following patch implements this, and at the same time corrects the wint_t
definition which is the same:

  /* Same for wint_t.  See SCD 2.4.1, p. 6-83, Figure 6-66 (32-bit).  There's
     no corresponding 64-bit definition, but this is what Solaris 8
     <iso/wchar_iso.h> uses.  */
  
  #undef WINT_TYPE
  #define WINT_TYPE (TARGET_64BIT ? "int" : "long int")

Clang :: Preprocessor/wchar_t.c and Clang :: Sema/format-strings.c need to
be adjusted to account for that.

Tested on i386-pc-solaris2.11, x86_64-pc-solaris2.11, and x86_64-pc-linux-gnu.

Differential Revision: https://reviews.llvm.org/D62944

llvm-svn: 363612
2019-06-17 20:21:25 +00:00
Hubert Tong a2c2d731db [CUDA] Fix grep pattern in cuda-types.cu
Summary:
vertical-line is not a BRE special character.

POSIX.1-2017 XBD Section 9.3.2 indicates that the interpretation of `\|`
is undefined. This patch uses EREs instead.

Additionally, the pattern is further fixed so that `SIZEOF` and `WIDTH`
macros are checked.

Reviewers: jlebar, daltenty, xingxue, jasonliu, tra

Reviewed By: tra

Subscribers: jfb, jsji, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D63029

llvm-svn: 362991
2019-06-10 22:28:20 +00:00
Sjoerd Meijer 4ea248eb56 [ARM] Add ACLE feature macros for MVE
If MVE is present at all, then the macro __ARM_FEATURE_MVE is defined
to a value which has bit 0 set for integer MVE, and bit 1 set for
floating-point MVE.

(Floating-point MVE implies integer MVE, so if this macro is defined
at all then it will be set to 1 or 3, never 2.)

Patch mostly by Simon Tatham

Differential Revision: https://reviews.llvm.org/D60710

llvm-svn: 362806
2019-06-07 15:20:56 +00:00
Simon Tatham 5d66f2b0af [ARM] Fix bugs introduced by the fp64/d32 rework.
Change D60691 caused some knock-on failures that weren't caught by the
existing tests. Firstly, selecting a CPU that should have had a
restricted FPU (e.g. `-mcpu=cortex-m4`, which should have 16 d-regs
and no double precision) could give the unrestricted version, because
`ARM::getFPUFeatures` returned a list of features including subtracted
ones (here `-fp64`,`-d32`), but `ARMTargetInfo::initFeatureMap` threw
away all the ones that didn't start with `+`. Secondly, the
preprocessor macros didn't reliably match the actual compilation
settings: for example, `-mfpu=softvfp` could still set `__ARM_FP` as
if hardware FP was available, because the list of features on the cc1
command line would include things like `+vfp4`,`-vfp4d16` and clang
didn't realise that one of those cancelled out the other.

I've fixed both of these issues by rewriting `ARM::getFPUFeatures` so
that it returns a list that enables every FP-related feature
compatible with the selected FPU and disables every feature not
compatible, which is more verbose but means clang doesn't have to
understand the dependency relationships between the backend features.
Meanwhile, `ARMTargetInfo::handleTargetFeatures` is testing for all
the various forms of the FP feature names, so that it won't miss cases
where it should have set `HW_FP` to feed into feature test macros.

That in turn caused an ordering problem when handling `-mcpu=foo+bar`
together with `-mfpu=something_that_turns_off_bar`. To fix that, I've
arranged that the `+bar` suffixes on the end of `-mcpu` and `-march`
cause feature names to be put into a separate vector which is
concatenated after the output of `getFPUFeatures`.

Another side effect of all this is to fix a bug where `clang -target
armv8-eabi` by itself would fail to set `__ARM_FEATURE_FMA`, even
though `armv8` (aka Arm v8-A) implies FP-Armv8 which has FMA. That was
because `HW_FP` was being set to a value including only the `FPARMV8`
bit, but that feature test macro was testing only the `VFP4FPU` bit.
Now `HW_FP` ends up with all the bits set, so it gives the right
answer.

Changes to tests included in this patch:

* `arm-target-features.c`: I had to change basically all the expected
  results. (The Cortex-M4 test in there should function as a
  regression test for the accidental double-precision bug.)
* `arm-mfpu.c`, `armv8.1m.main.c`: switched to using `CHECK-DAG`
  everywhere so that those tests are no longer sensitive to the order
  of cc1 feature options on the command line.
* `arm-acle-6.5.c`: been updated to expect the right answer to that
  FMA test.
* `Preprocessor/arm-target-features.c`: added a regression test for
  the `mfpu=softvfp` issue.

Reviewers: SjoerdMeijer, dmgreen, ostannard, samparker, JamesNagurne

Reviewed By: ostannard

Subscribers: srhines, javed.absar, kristof.beyls, hiraditya, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D62998

llvm-svn: 362791
2019-06-07 12:42:54 +00:00
Pengfei Wang 30bcda86db [X86] -march=cooperlake (clang)
Support intel -march=cooperlake in clang

Patch by Shengchen Kan (skan)

Differential Revision: https://reviews.llvm.org/D62835

llvm-svn: 362781
2019-06-07 08:53:37 +00:00
Pengfei Wang 3a29f7c99c [X86] Add ENQCMD instructions
For more details about these instructions, please refer to the latest
ISE document:
https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference.

Patch by Tianqing Wang (tianqing)

Differential Revision: https://reviews.llvm.org/D62282

llvm-svn: 362685
2019-06-06 08:28:42 +00:00