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115 Commits

Author SHA1 Message Date
Evan Cheng bf4070756f Teach if-converter to be more careful with predicating instructions that would 
take multiple cycles to decode.
For the current if-converter clients (actually only ARM), the instructions that
are predicated on false are not nops. They would still take machine cycles to
decode. Micro-coded instructions such as LDM / STM can potentially take multiple
cycles to decode. If-converter should take treat them as non-micro-coded
simple instructions.

llvm-svn: 113570
 2010-09-10 01:29:16 +00:00
Owen Anderson a7aed18624 Reapply r110396, with fixes to appease the Linux buildbot gods. 
llvm-svn: 110460
 2010-08-06 18:33:48 +00:00
Owen Anderson bda59bd247 Revert r110396 to fix buildbots. 
llvm-svn: 110410
 2010-08-06 00:23:35 +00:00
Owen Anderson 755aceb5d0 Don't use PassInfo* as a type identifier for passes. Instead, use the address of the static 
ID member as the sole unique type identifier.  Clean up APIs related to this change.

llvm-svn: 110396
 2010-08-05 23:42:04 +00:00
Bill Wendling dd5e9d8faf Use std::vector instead of TargetRegisterInfo::FirstVirtualRegister. 
llvm-svn: 108450
 2010-07-15 20:01:02 +00:00
Evan Cheng 2d51c7c592 Allow ARM if-converter to be run after post allocation scheduling. 
- This fixed a number of bugs in if-converter, tail merging, and post-allocation
  scheduler. If-converter now runs branch folding / tail merging first to
  maximize if-conversion opportunities.
- Also changed the t2IT instruction slightly. It now defines the ITSTATE
  register which is read by instructions in the IT block.
- Added Thumb2 specific hazard recognizer to ensure the scheduler doesn't
  change the instruction ordering in the IT block (since IT mask has been
  finalized). It also ensures no other instructions can be scheduled between
  instructions in the IT block.

This is not yet enabled.

llvm-svn: 106344
 2010-06-18 23:09:54 +00:00
Evan Cheng 078f4cec21 - Do away with SimpleHazardRecognizer.h. It's not used and offers little value. 
- Rename ExactHazardRecognizer to PostRAHazardRecognizer and move its header to include to allow targets to extend it.

llvm-svn: 105959
 2010-06-14 21:06:53 +00:00
Evan Cheng e60273fd70 Allow target to provide its own hazard recognizer to post-ra scheduler. 
llvm-svn: 105862
 2010-06-12 00:12:18 +00:00
Evan Cheng 3858451e09 - Change MachineInstr::findRegisterDefOperandIdx so it can also look for defs 
that are aliases of the specified register.
- Rename modifiesRegister to definesRegister since it's looking a def of the
specific register or one of its super-registers. It's not looking for def of a
sub-register or alias that could change the specified register.
- Added modifiesRegister to look for defs of aliases.

llvm-svn: 104377
 2010-05-21 20:53:24 +00:00
Jim Grosbach 63d4f68df4 Remove dbg_value workaround and associated command line option 
llvm-svn: 104254
 2010-05-20 18:34:01 +00:00
Jim Grosbach f98511473e Enable preserving debug information through post-RA scheduling 
llvm-svn: 104175
 2010-05-19 22:57:47 +00:00
Jim Grosbach d772bdeb7e 80 column and trailing whitespace cleanup 
llvm-svn: 103806
 2010-05-14 21:19:48 +00:00
Jim Grosbach 25749ad5c2 add cmd line option to leave dbgvalues in during post-RA sceduling. Useful 
while debugging what's mishandled about them in the post-RA pass.

llvm-svn: 103805
 2010-05-14 21:18:04 +00:00
Dan Gohman 25c1653700 Get rid of the EdgeMapping map. Instead, just check for BasicBlock 
changes before doing phi lowering for switches.

llvm-svn: 102809
 2010-05-01 00:01:06 +00:00
Bob Wilson 4e5eb5ae1b As a temporary workaround for post-RA not handling DebugValue instructions, 
just remove them all.  Radar 7873207 (working around the root problem of
Radar 7759363).

llvm-svn: 101604
 2010-04-17 00:49:11 +00:00
Dan Gohman e4148978b8 Remove a #include. 
llvm-svn: 101043
 2010-04-12 16:26:03 +00:00
Dale Johannesen 2061c84109 Fix some more places where dbg_value affected codegen. 
llvm-svn: 97765
 2010-03-05 00:02:59 +00:00
David Greene aa8ce38113 Change errs() to dbgs(). 
llvm-svn: 92594
 2010-01-05 01:26:01 +00:00
David Goodwin a45fe67667 <rdar://problem/7453528>. Track only physical registers that are valid for the target. 
llvm-svn: 90970
 2009-12-09 17:18:22 +00:00
Jakob Stoklund Olesen 8392456f1b Don't hang on to pointers or references after vector::push_back. 
The MO reference to a MachineOperand can be invalidated by
MachineInstr::addOperand. Don't even use it for debugging.

llvm-svn: 90381
 2009-12-03 01:49:56 +00:00
David Goodwin 80a03cc0b1 Remove some old experimental code that is no longer needed. Remove additional, speculative scheduling pass as its cost did not translate into significant performance improvement. Minor tweaks. 
llvm-svn: 89471
 2009-11-20 19:32:48 +00:00
David Goodwin b9fe5d5d02 Allow target to specify regclass for which antideps will only be broken along the critical path. 
llvm-svn: 88682
 2009-11-13 19:52:48 +00:00
David Goodwin da83f7d58b Rename registers to break output dependencies in addition to anti-dependencies. 
llvm-svn: 87015
 2009-11-12 19:08:21 +00:00
David Goodwin 0d412c2528 Fixed to address code review. No functional changes. 
llvm-svn: 86634
 2009-11-10 00:48:55 +00:00
David Goodwin cf89db135e Allow targets to specify register classes whose member registers should not be renamed to break anti-dependencies. 
llvm-svn: 86628
 2009-11-10 00:15:47 +00:00