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7c277da364716fdfd16d11bcbc26463e8ffe20b1
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214 Commits

Author SHA1 Message Date
Nadav Rotem 7c277da364 Add a new optimization pass: Stack Coloring, that merges disjoint static allocations (allocas). Allocas are known to be 
disjoint if they are marked by disjoint lifetime markers (@llvm.lifetime.XXX intrinsics).

llvm-svn: 163299
 2012-09-06 09:17:37 +00:00
Jakob Stoklund Olesen 9dc03bba14 Add CodeGenTarget::guessInstructionProperties. 
Currently, TableGen just guesses instruction properties when it can't
infer them form patterns.

This adds a guessInstructionProperties flag to the instruction set
definition that will be used to disable guessing. The flag is intended
as a migration aid. It will be removed again when no more targets need
their properties guessed.

llvm-svn: 162460
 2012-08-23 19:34:41 +00:00
Andrew Trick 87255e340e I'm introducing a new machine model to simultaneously allow simple 
subtarget CPU descriptions and support new features of
MachineScheduler.

MachineModel has three categories of data:
1) Basic properties for coarse grained instruction cost model.
2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD).
3) Instruction itineraties for detailed per-cycle reservation tables.

These will all live side-by-side. Any subtarget can use any
combination of them. Instruction itineraries will not change in the
near term. In the long run, I expect them to only be relevant for
in-order VLIW machines that have complex contraints and require a
precise scheduling/bundling model. Once itineraries are only actively
used by VLIW-ish targets, they could be replaced by something more
appropriate for those targets.

This tablegen backend rewrite sets things up for introducing
MachineModel type #2: per opcode/operand cost model.

llvm-svn: 159891
 2012-07-07 04:00:00 +00:00
Andrew Trick 91118a6155 whitespace 
llvm-svn: 159890
 2012-07-07 03:59:51 +00:00
Chris Lattner ff9e08baf9 rdar://11542750 - llvm.trap should be marked no return. 
llvm-svn: 157551
 2012-05-27 23:20:41 +00:00
Jim Grosbach 53733cdb23 Revert "Emit the SubRegTable with the smallest possible integer type." 
This reverts commit 151760.

We want to move getSubReg() from TargetRegisterInfo into MCRegisterInfo,
but to do that, the type of the lookup table needs to be the same for
all targets.

llvm-svn: 151814
 2012-03-01 17:30:35 +00:00
Benjamin Kramer c80c3fd5a7 Emit the SubRegTable with the smallest possible integer type. 
Doesn't help ARM with its massive register set, but halves the size on x86 and all other targets.

llvm-svn: 151760
 2012-02-29 21:57:08 +00:00
Craig Topper c4965bce14 Convert assert(0) to llvm_unreachable 
llvm-svn: 149814
 2012-02-05 07:21:30 +00:00
Pete Cooper 9bcb72136e Added MVT::v2f16 
llvm-svn: 148067
 2012-01-12 23:14:13 +00:00
Devang Patel 85d684a4d9 Split AsmParser into two components - AsmParser and AsmParserVariant 
AsmParser holds info specific to target parser.
AsmParserVariant holds info specific to asm variants supported by the target.

llvm-svn: 147787
 2012-01-09 19:13:28 +00:00
Dan Gohman 94580ab375 Add basic generic CodeGen support for half. 
llvm-svn: 146927
 2011-12-20 00:02:33 +00:00
Evan Cheng 2a81dd4a3c First chunk of MachineInstr bundle support. 
1. Added opcode BUNDLE
2. Taught MachineInstr class to deal with bundled MIs
3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs
4. Taught MachineBasicBlock methods about bundled MIs

llvm-svn: 145975
 2011-12-06 22:12:01 +00:00
Owen Anderson ca2f78a95b Rename MVT::untyped to MVT::Untyped to match similar nomenclature. 
llvm-svn: 144747
 2011-11-16 01:02:57 +00:00
Peter Collingbourne 84c287e33c Move TableGen's parser and entry point into a library 
This is the first step towards splitting LLVM and Clang's tblgen executables.

llvm-svn: 140951
 2011-10-01 16:41:13 +00:00
Jakob Stoklund Olesen 19be2ab320 Switch to ArrayRef<CodeGenRegisterClass*>. 
This makes it possible to allocate CodeGenRegisterClass instances
dynamically and reorder them.

llvm-svn: 140816
 2011-09-29 22:28:37 +00:00
David Greene af8ee2cdee Unconstify Inits 
Remove const qualifiers from Init references, per Chris' request.

llvm-svn: 136531
 2011-07-29 22:43:06 +00:00
David Greene 1aa0e3e118 [AVX] Constify Inits 
Make references to Inits const everywhere.  This is the final step
before making them unique.

llvm-svn: 136485
 2011-07-29 19:07:05 +00:00
Eric Christopher 71520a867d Revert r134921, 134917, 134908 and 134907. They're causing failures 
in multiple buildbots.

llvm-svn: 134936
 2011-07-11 23:06:52 +00:00
David Greene af973b4f36 [AVX] Make Inits Foldable 
Manage Inits in a FoldingSet.  This provides several benefits:

- Memory for Inits is properly managed

- Duplicate Inits are folded into Flyweights, saving memory

- It enforces const-correctness, protecting against certain classes
  of bugs

The above benefits allow Inits to be used in more contexts, which in
turn provides more dynamism to TableGen.  This enhanced capability
will be used by the AVX code generator to a fold common patterns
together.

llvm-svn: 134907
 2011-07-11 18:25:51 +00:00
Owen Anderson a84be6c96b Add support for alternative register names, useful for instructions whose operands are logically equivalent to existing registers, but happen to be printed specially. For example, an instruciton that prints d0[0] instead of s0. 
Patch by Jim Grosbach.

llvm-svn: 133940
 2011-06-27 21:06:21 +00:00
Jakob Stoklund Olesen 8e188be035 Store CodeGenRegisters as pointers so they won't be reallocated. 
Reuse the CodeGenRegBank DenseMap in a few places that would build their
own or use linear search.

llvm-svn: 133333
 2011-06-18 04:26:06 +00:00
Owen Anderson f5a0ca46b6 Fix formatting. 
llvm-svn: 133164
 2011-06-16 16:52:24 +00:00
Owen Anderson 96adc4a540 Add a new MVT::untyped. This will be used in future work for modelling ISA features like register pairs and lists with "interesting" constraints (such as ARM NEON contiguous register lists or even-odd paired registers). We need to be able to generate these instructions (often from intrinsics), but don't want to have to assign a legal type to them. Instead, we'll use an "untyped" edge to bypass the type-checking and simply ensure that the register classes match. 
llvm-svn: 133106
 2011-06-15 23:35:18 +00:00
Jakob Stoklund Olesen d7bc5c26ab Give CodeGenRegisterClass a real sorted member set. 
Make the Elements vector private and expose an ArrayRef through
getOrder() instead. getOrder will eventually provide multiple
user-specified allocation orders.

Use the sorted member set for member and subclass tests. Clean up a lot
of ad hoc searches.

llvm-svn: 133040
 2011-06-15 04:50:36 +00:00
Jakob Stoklund Olesen 22ea424d43 Move the list of register classes into CodeGenRegBank as well. 
No functional change intended.

llvm-svn: 133029
 2011-06-15 00:20:40 +00:00