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57 Commits

Author SHA1 Message Date
Gerolf Hoflehner caa8bfd13b [Cleanup] Utility function to erase instruction and mark DBG_Values 
New function to erase a machine instruction and mark DBG_VALUE
for removal. A DBG_VALUE is marked for removal when it references
an operand defined in the instruction.
Use the new function to cleanup code in dead machine instruction
removal pass.

llvm-svn: 215580
 2014-08-13 21:15:23 +00:00
Eric Christopher fc6de428c8 Have MachineFunction cache a pointer to the subtarget to make lookups 
shorter/easier and have the DAG use that to do the same lookup. This
can be used in the future for TargetMachine based caching lookups from
the MachineFunction easily.

Update the MIPS subtarget switching machinery to update this pointer
at the same time it runs.

llvm-svn: 214838
 2014-08-05 02:39:49 +00:00
Eric Christopher d913448b38 Remove the TargetMachine forwards for TargetSubtargetInfo based 
information and update all callers. No functional change.

llvm-svn: 214781
 2014-08-04 21:25:23 +00:00
Chandler Carruth 1b9dde087e [Modules] Remove potential ODR violations by sinking the DEBUG_TYPE 
define below all header includes in the lib/CodeGen/... tree. While the
current modules implementation doesn't check for this kind of ODR
violation yet, it is likely to grow support for it in the future. It
also removes one layer of macro pollution across all the included
headers.

Other sub-trees will follow.

llvm-svn: 206837
 2014-04-22 02:02:50 +00:00
Craig Topper c0196b1b40 [C++11] More 'nullptr' conversion. In some cases just using a boolean check instead of comparing to nullptr. 
llvm-svn: 206142
 2014-04-14 00:51:57 +00:00
Paul Robinson 7c99ec5b99 Disable each MachineFunctionPass for 'optnone' functions, unless that 
pass normally runs at optimization level None, or is part of the
register allocation pipeline.

llvm-svn: 205228
 2014-03-31 17:43:35 +00:00
Ekaterina Romanova 8d62008ecb Fix for http://llvm.org/bugs/show_bug.cgi?id=18590 
This patch fixes the bug in peephole optimization that folds a load which defines one vreg into the one and only use of that vreg. With debug info, a DBG_VALUE that referenced the vreg considered to be a use, preventing the optimization. The fix is to ignore DBG_VALUE's during the optimization, and undef a DBG_VALUE that references a vreg that gets removed.
Patch by Trevor Smigiel!

llvm-svn: 203829
 2014-03-13 18:47:12 +00:00
Craig Topper 4584cd54e3 [C++11] Add 'override' keyword to virtual methods that override their base class. 
llvm-svn: 203220
 2014-03-07 09:26:03 +00:00
Benjamin Kramer b6d0bd48bd [C++11] Replace llvm::next and llvm::prior with std::next and std::prev. 
Remove the old functions.

llvm-svn: 202636
 2014-03-02 12:27:27 +00:00
Chad Rosier abdb1d69ab Simplify logic now that r182490 is in place. No functional change intended. 
llvm-svn: 182531
 2013-05-22 23:17:36 +00:00
Jakob Stoklund Olesen c338679c9d Remove special-casing of return blocks for liveness. 
Now that return value registers are return instruction uses, there is no
need for special treatment of return blocks.

llvm-svn: 174416
 2013-02-05 18:21:52 +00:00
Chandler Carruth ed0881b2a6 Use the new script to sort the includes of every file under lib. 
Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.

Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]

llvm-svn: 169131
 2012-12-03 16:50:05 +00:00
Jakob Stoklund Olesen c30a9af2d7 Switch most getReservedRegs() clients to the MRI equivalent. 
Using the cached bit vector in MRI avoids comstantly allocating and
recomputing the reserved register bit vector.

llvm-svn: 165983
 2012-10-15 21:57:41 +00:00
Jakob Stoklund Olesen 54038d796c Switch all register list clients to the new MC*Iterator interface. 
No functional change intended.

Sorry for the churn. The iterator classes are supposed to help avoid
giant commits like this one in the future. The TableGen-produced
register lists are getting quite large, and it may be necessary to
change the table representation.

This makes it possible to do so without changing all clients (again).

llvm-svn: 157854
 2012-06-01 23:28:30 +00:00
Jakob Stoklund Olesen 92a0083944 Switch some getAliasSet clients to MCRegAliasIterator. 
MCRegAliasIterator can optionally visit the register itself, allowing
for simpler code.

llvm-svn: 157837
 2012-06-01 20:36:54 +00:00
Craig Topper 4b02a29eba Convert more GenRegisterInfo tables from unsigned to uint16_t to reduce static data size. 
llvm-svn: 152016
 2012-03-05 05:37:41 +00:00
Craig Topper 1d32658877 Use uint16_t to store register overlaps to reduce static data. 
llvm-svn: 152001
 2012-03-04 10:43:23 +00:00
Jakob Stoklund Olesen 5d33291e8e Never delete instructions that define reserved registers. 
I think this was already the intention, but DeadMachineInstructionElim
was accidentally tracking the liveness of reserved registers. Now,
instructions with reserved defs are never deleted.

This prevents the call stack adjustment instructions from getting
deleted when enabling register masks.

llvm-svn: 150116
 2012-02-09 00:15:39 +00:00
Andrew Trick 1fa5bcbe2a Codegen pass definition cleanup. No functionality. 
Moving toward a uniform style of pass definition to allow easier target configuration.
Globally declare Pass ID.
Globally declare pass initializer.
Use INITIALIZE_PASS consistently.
Add a call to the initializer from CodeGen.cpp.
Remove redundant "createPass" functions and "getPassName" methods.

While cleaning up declarations, cleaned up comments (sorry for large diff).

llvm-svn: 150100
 2012-02-08 21:23:13 +00:00
Andrew Trick 9e761997d8 whitespace 
llvm-svn: 150094
 2012-02-08 21:22:43 +00:00
Jakob Stoklund Olesen 5e1ac45b93 Require non-NULL register masks. 
It doesn't seem worthwhile to give meaning to a NULL register mask
pointer. It complicates all the code using register mask operands.

llvm-svn: 149646
 2012-02-02 23:52:57 +00:00
Jakob Stoklund Olesen 58614f2f5a Handle register masks in DeadMachineInstructionElim. 
Don't track live physregs that are clobbered by a register mask operand.

llvm-svn: 148588
 2012-01-20 22:27:09 +00:00
Evan Cheng 7f8e563a69 Add bundle aware API for querying instruction properties and switch the code 
generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.

For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.

llvm-svn: 146026
 2011-12-07 07:15:52 +00:00
Jakob Stoklund Olesen 79f1b714a2 Track live-out physical registers in MachineDCE. 
Patch by Sanjoy Das!

llvm-svn: 133910
 2011-06-27 15:00:36 +00:00
Jakob Stoklund Olesen 2fb5b31578 Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic. 
These functions not longer assert when passed 0, but simply return false instead.

No functional change intended.

llvm-svn: 123155
 2011-01-10 02:58:51 +00:00