When built in SEH mode, UnwindCursor contains a CONTEXT struct,
which is aligned to 16 bytes in most configurations, causing the
whole UnwindCursor object to have 16 byte alignment.
This fixes backtraces using _Unwind_Backtrace on x86_64 mingw,
where an unw_cursor_t allocated on the stack was misaligned before.
This is an ABI break for this struct for this configuration, but very
few callers call libunwind directly (and even fewer directly allocate
an unw_cursor_t anyway).
Differential Revision: https://reviews.llvm.org/D86102
This patch renames `__personality_routine` to `_Unwind_Personality_Fn`
in `unwind.h`. Both `unwind.h` from clang and GCC headers use this name
instead of `__personality_routine`. With this patch one is also able to
build libc++abi with libunwind support on Windows.
Patch by Markus Böck!
Summary:
Add unwinding support for 64-bit RISC-V.
This is from the FreeBSD implementation with the following minor
changes:
- Renamed and renumbered DWARF registers to match the RISC-V ABI [1]
- Use the ABI mneumonics in getRegisterName() instead of the exact
register names
- Include checks for __riscv_xlen == 64 to facilitate adding the 32-bit
ABI in the future.
[1] https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md
Patch by Mitchell Horne (mhorne)
Reviewers: lenary, luismarques, compnerd, phosek
Reviewed By: lenary, luismarques
Subscribers: arichardson, sameer.abuasal, abidh, asb, aprantl, krytarowski, simoncook, kito-cheng, christof, shiva0217, rogfer01, rkruppe, PkmX, psnobl, benna, lenary, s.egerton, luismarques, emaste, cfe-commits
Differential Revision: https://reviews.llvm.org/D68362
This is unfinished, unused and incomplete. This could be brought back in
the future if there's a desire to build a more complete implementation,
but at the moment it's just bitrotting.
Differential Revision: https://reviews.llvm.org/D57252
llvm-svn: 352965
The existing typedef of unw_fpreg_t to uint64_t might work and be
correct for the ARM_EHABI case, but for dwarf, some cases in e.g.
DwarfInstructions.hpp convert between double and unw_fpreg_t.
When converting implicitly between double and unw_fpreg_t (uint64_t),
the values get interpreted as integers and converted to float and vice
versa, while the correct thing would be to keep the same bit pattern.
Avoid the whole issue by using the same definition of unw_fpreg_t
as all other architectures, when using dwarf unwinding on ARM.
Change assembler functions to take a void pointer instead of
unw_fpreg_t pointer, to avoid having a different mangled symbol name
depending on the actual value of this typedef.
Differential Revision: https://reviews.llvm.org/D57001
llvm-svn: 352461
to reflect the new license. These used slightly different spellings that
defeated my regular expressions.
We understand that people may be surprised that we're moving the header
entirely to discuss the new license. We checked this carefully with the
Foundation's lawyer and we believe this is the correct approach.
Essentially, all code in the project is now made available by the LLVM
project under our new license, so you will see that the license headers
include that license only. Some of our contributors have contributed
code under our old license, and accordingly, we have retained a copy of
our old license notice in the top-level files in each project and
repository.
llvm-svn: 351648
Summary:
Adds the register class implementation for Sparc.
Adds support for DW_CFA_GNU_window_save.
Adds save and restore context functionality.
Adds getArch() function to each Registers_ class to be able to separate
between DW_CFA_AARCH64_negate_ra_state and DW_CFA_GNU_window_save which
are both represented by the same constant.
On Sparc the return address is the address of the call instruction, so
an offset needs to be added when returning to skip the call instruction
and its delay slot. If the function returns a struct it is also necessary
to skip one extra instruction on Sparc V8.
Reviewers: jyknight, mclow.lists, mstorsjo, compnerd
Reviewed By: jyknight, compnerd
Subscribers: jgorbe, mgorny, christof, llvm-commits, fedor.sergeev, JDevlieghere, ldionne, libcxx-commits
Differential Revision: https://reviews.llvm.org/D55763
llvm-svn: 351044
Summary:
Adds the register class implementation for Sparc.
Adds support for DW_CFA_GNU_window_save.
Adds save and restore context functionality.
On Sparc the return address is the address of the call instruction,
so an offset needs to be added when returning to skip the call instruction
and its delay slot. If the function returns a struct it is also necessary
to skip one extra instruction.
Reviewers: jyknight, mclow.lists, mstorsjo, compnerd
Reviewed By: compnerd
Subscribers: fedor.sergeev, JDevlieghere, ldionne, libcxx-commits
Differential Revision: https://reviews.llvm.org/D55763
llvm-svn: 350705
This doesn't yet implement inspecting the .pdata/.xdata to find the
LSDA pointer (in UnwindCursor::getInfoFromSEH), but normal C++
exception handling seems to run just fine without it. (The only
place I can see where it's even referenced is in
unwind_phase2_forced, and I can't find a codepath where libcxxabi
would end up calling that.)
Differential Revision: https://reviews.llvm.org/D55674
llvm-svn: 349532
- Follow up to revision r342895
- gcc would not build libunwind with the earlier patch as the autia1716
instruction wasn't allowed to be assembled for pre armv8.3a targets
- The autia1716 instruction lives in the hint space encodings so is a valid
instruction for all armv8a targets
- To work around this I have swapped out the autia1716 instruction for the hint
instruction
Differential Revision: https://reviews.llvm.org/D55700
llvm-svn: 349140
- When return address signing is enabled, the LR may be signed on function entry
- When an exception is thrown the return address is inspected used to unwind the call stack
- Before this happens, the return address must be correctly authenticated to avoid causing an abort by dereferencing the signed pointer
Differential Revision: https://reviews.llvm.org/D51432
llvm-svn: 342895
Even though SEH for ARM is incomplete, make what code already exists
at least compile correctly.
The _LIBUNWIND_CURSOR_SIZE wasn't correct.
ARM (and AArch64) have a DISPATCHER_CONTEXT field named TargetPc
instead of TargetIp.
For the libunwind.h UNW_* constants, there is no UNW_ARM_PC, only
UNW_ARM_IP.
Don't use 'r' as loop variable when 'r' already is a Registers_arm
member.
Differential Revision: https://reviews.llvm.org/D51530
llvm-svn: 341217
Summary:
I've tested this implementation on x86-64 to ensure that it works. All
`libc++abi` tests pass, as do all `libc++` exception-related tests. ARM
still remains to be implemented (@compnerd?).
Special thanks to KJK::Hyperion for his excellent series of articles on
how EH works on x86-64 Windows. (Seriously, check it out. It's awesome.)
I'm actually not sure if this should go in as is. I particularly don't
like that I duplicated the UnwindCursor class for this special case.
Reviewers: mstorsjo, rnk, compnerd, smeenai, javed.absar
Subscribers: mgorny, kristof.beyls, christof, chrib, cfe-commits, compnerd, llvm-commits
Differential Revision: https://reviews.llvm.org/D50564
llvm-svn: 341125
Summary:
Make the `_Unwind_Exception` struct correct under SEH. Add a
declaration of `_GCC_specific_handler()`, which is used by SEH versions
of Itanium personality handlers to do common setup. Roughly corresponds
to Clang's D50380.
Reviewers: mstorsjo, rnk, compnerd, smeenai
Subscribers: christof, chrib, cfe-commits, llvm-commits
Differential Revision: https://reviews.llvm.org/D50414
llvm-svn: 339258
This makes it possible to unwind hardware exception stack frames,
which necessarily save every register and so need an extra column
for storing the return address. CFI for the exception handler could
then look as follows:
.globl exception_vector
exception_vector:
.cfi_startproc
.cfi_signal_frame
.cfi_return_column 32
l.addi r1, r1, -0x100
.cfi_def_cfa_offset 0x100
l.sw 0x00(r1), r2
.cfi_offset 2, 0x00-0x100
l.sw 0x04(r1), r3
.cfi_offset 3, 0x04-0x100
l.sw 0x08(r1), r4
.cfi_offset 4, 0x08-0x100
l.mfspr r3, r0, SPR_EPCR_BASE
l.sw 0x78(r1), r3
.cfi_offset 32, 0x78-0x100
l.jal exception_handler
l.nop
l.lwz r2, 0x00(r1)
l.lwz r3, 0x04(r1)
l.lwz r4, 0x08(r1)
l.jr r9
l.nop
.cfi_endproc
This register could, of course, also be accessed by the trace
callback or personality function, if so desired.
llvm-svn: 332513
Summary:
For MIPS ABIs with 64-bit floating point registers including newabi
and O32 with 64-bit floating point registers, just save and restore the
32 floating-point registers as doubles.
For O32 MIPS with 32-bit floating-point registers, save and restore the
individual floating-point registers as "plain" registers. These registers
are encoded as floats rather than doubles, but the DWARF unwinder
assumes that floating-point registers are stored as doubles when reading
them from memory (via AddressSpace::getDouble()). Treating the
registers as "normal" registers instead causes the DWARF unwinder to
fetch them from memory as a 32-bit register. This does mean that for
O32 with 32-bit floating-point registers unw_get_fpreg() and
unw_set_fpreg() do not work. One would have to use unw_get_reg()
and unw_set_reg() instead. However, DWARF unwinding works
correctly as the DWARF CFI emits records for individual 32-bit
floating-point registers even when they are treated as doubles stored
in paired registers. If the lack of unw_get/set_fpreg() becomes a pressing
need in the future for O32 MIPS we could add in special handling to
make it work.
Reviewers: sdardis, compnerd
Reviewed By: sdardis
Differential Revision: https://reviews.llvm.org/D41968
llvm-svn: 332414
Summary:
N32 uses the same register context as N64. However, N32 requires one
change to properly fetch addresses from registers stored in memory.
Since N32 is an ILP32 platform, getP() only fetches the first 32-bits
of a stored register. For a big-endian platform this fetches the
upper 32-bits which will be zero. To fix this, add a new
getRegister() method to AddressSpace which is responsible for
extracting the address stored in a register in memory. This matches
getP() for all current ABIs except for N32 where it reads the 64-bit
register and returns the low 32-bits as an address. The
DwarfInstructions::getSavedRegister() method uses
AddressSpace::getRegister() instead of AddressSpace::getP().
Reviewers: sdardis, compnerd
Reviewed By: sdardis
Differential Revision: https://reviews.llvm.org/D39074
llvm-svn: 326250
The Registers_ppc64 class needed a couple of changes, both to accommodate the
new registers as well as to handle the overlaps of VS register set
without wasting space.
The save/restore code of V and VS registers was added.
As VS registers depend on the VMX extension, they are processed only if
VMX support is detected (_ARCH_PWR8 for now).
Patch by Leandro Lupori!
Differential Revision: https://reviews.llvm.org/D41906
llvm-svn: 322596
This is in preparation for adding support for N32 unwinding which reuses
the newabi register class.
Reviewed By: compnerd
Differential Revision: https://reviews.llvm.org/D41842
llvm-svn: 322093
Initial working version of libunwind for PowerPC 64. Tested on
little-endian ppc64 host only.
Based on the existing PowerPC 32 code.
It supports:
- context save/restore (unw_getcontext, unw_init_local, unw_resume)
- read/write from/to saved registers
- backtrace (unw_step)
Patch by Leandro Lupori!
Differential Revision: https://reviews.llvm.org/D41386
Now builds with LIBUNWIND_ENABLE_CROSS_UNWINDING=ON should
work.
llvm-svn: 321680
Martin Storsjö
Brian Cain
Saleem Abdulrasool
Sam Elliott
Louis Dionne
Petr Hosek
Chandler Carruth
Daniel Cederman
Jorge Gorbe Moya
Luke Cheeseman
Charles Davis
whitequark
John Baldwin