This patch seems to have originally been from
https://patchwork.coreboot.org/patch/4126/ . The most recent version
seems to be in OpenEmbedded (commit 503a572) which added support for
16Mbit and 32Mbit variants.
The OpenEmbedded patch also makes changes to linux_spi.c to add some
debug prints which are omitted in this version.
From the original commit message:
Differences between SST26 and SST25:
1. The WREN instruction must be executed prior to WRSR [Section 5.31].
There is no EWSR.
2. Block protection bits are no longer in the status register. There
is a dedicated 144-bit register [Table 5-6]. The device is
write-protected by default. A Global Block-Protection Unlock
command unlocks the entire memory [Section 4.1].
Change-Id: Ib019bed8ce955049703eb3376c32a83ef607c219
Signed-off-by: Wei Hu <wei@aristanetworks.com>
Signed-off-by: David Hendricks <david.hendricks@gmail.com>
Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at>
Reviewed-on: https://review.coreboot.org/25962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The ENE Embedded Debug Interface (EDI) is a SPI-based interface for
accessing the memory of ENE embedded controllers.
The ENE KB9012 EC is an embedded controller found on various laptops
such as the Lenovo G505s. It features a 8051 microcontroller and
has 128 KiB of internal storage for program data.
EDI can be accessed on the KB9012 through pins 59-62 (CS-CLK-MOSI-MISO)
when flash direct access is not in use. Some firmwares disable EDI at runtime
so it might be necessary to ground pin 42 to reset the 8051 microcontroller
before accessing the KB9012 via EDI.
The example of flashing KB9012 at Lenovo G505S laptop could be found here:
http://dangerousprototypes.com/docs/Flashing_KB9012_with_Bus_Pirate
Change-Id: Ib8b2eb2feeef5c337d725d15ebf994a299897854
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/23259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Instead of arbitrarily deciding whether to enter 4BA mode in the flash
chip's declaration, advertise that entering 4BA mode is supported and
only enter it if the SPI master supports 4-byte addresses. If not, exit
4BA mode (the chip might be in 4BA mode after reset). If we can't assure
the state of 4BA mode, we bail out to simplify the code (we'd have to
ensure that we don't run any instructions that can usually be switched
to 4BA mode otherwise).
Two new feature flags are introduced:
* FEATURE_4BA_ENTER:
Can enter/exit 4BA mode with instructions 0xb7/0xe9 w/o WREN.
* FEATURE_4BA_ENTER_WREN
Can enter/exit 4BA mode with instructions 0xb7/0xe9 after WREN.
FEATURE_4BA_SUPPORT is dropped, it's completely implicit now.
Also, draw the with/without WREN distinction into the enter/exit
functions to reduce code redundancy.
Change-Id: I877fe817f801fc54bd0ee2ce4e3ead324cbb3673
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/22422
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Introduce spi_prepare_address() and spi_write_cmd() and use them in
nbyte_program, nbyte_read and block-erase procedures. The former
abstracts over the address part of a SPI command to make it exten-
sible for 4-byte adressing. spi_write_cmd() implements a WREN + write
operation with address and optionally up to 256 bytes of data. It
provides a common path to reduce overall redundancy.
Also, reduce the polling delay in spi_block_erase_c4() from 500s to
500ms as the comment suggests.
Change-Id: Ibc1ae48acbfbd427a30bcd64bdc080dc3dc20503
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/22383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Large flash chips usually support special instructions to work with
4-bytes address directly from 3-bytes addressing mode and without
do switching to 4-bytes mode. There are 13h (4BA Read), 12h (4BA Program)
and 21h,5Ch,DCh (4BA Erase), correspondingly. However not all these
instructions are supported by all large flash chips. Some chips
support 13h only, some 13h,12h,21h and DCh, but not 5Ch. This depends
on the manufacturer of the chip.
This patch provides code to use direct 4-bytes addressing instructions.
This code should work but it tested partially only. My W25Q256FV has
support for 4BA_Read (13h), but doesn't have support 4BA_Program (12h)
and 4BA_Erase instructions. So, direct 4BA program and erase
should be tested after.
Patched files
-------------
chipdrivers.h
+ added functions declarations for spi4ba.c
flash.h
+ feature definitions added
flashchips.c
+ modified definition of Winbond W25Q256BV/W25Q256FV chips
flashrom.c
+ modified switch to 4-bytes addressing for direct-4BA instructions
spi4ba.h
+ definitions for 4-bytes addressing JEDEC commands
+ functions declarations from spi4ba.c (same as in chipdrivers.h, just to see)
spi4ba.c
+ functions for read/write/erase directly with 4-bytes address (from any mode)
Change-Id: Ib51bcc5de7826b30ad697fcbb9a5152bde2c2ac9
Signed-off-by: Boris Baykov <dev@borisbaykov.com>, Russia, Jan 2014
[clg: ported from
https://www.flashrom.org/pipermail/flashrom/2015-January/013198.html ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-on: https://review.coreboot.org/20508
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On some flash chips data with addresses more than 24-bit field
can address may be accessed by using Extended Address Register.
The register has 1-byte size and stores high byte of 32-bit address.
Then flash can be read from 3-bytes addressing mode with writing
high byte of address to this Register. By using this way we have
access to full memory of a chip. Some chips may support this method
only.
This patch provides code use Extended Address Register.
Patched files
-------------
chipdrivers.h
+ added functions declarations for spi4ba.c
flash.h
+ feature definitions added
flashrom.c
+ modified switch to 4-bytes addressing to support extended address register
spi4ba.h
+ definitions for 4-bytes addressing JEDEC commands
+ functions declarations from spi4ba.c (same as in chipdrivers.h, just to see)
spi4ba.c
+ functions for write Extended Address Register
+ functions for read/write/erase with Extended Address Register
Change-Id: I09a8aa11de2ca14901f142c67c83c4fa0def4e27
Signed-off-by: Boris Baykov <dev@borisbaykov.com>, Russia, Jan 2014
[clg: ported from
https://www.flashrom.org/pipermail/flashrom/2015-January/013200.html ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-on: https://review.coreboot.org/20507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
If flash chip is switched to 4-bytes addressing mode then all
read/erase/program instructions will be switched from 3-bytes mode
to 4-bytes mode. Then well known instructions like 03h (Read),
02h (Program) and 20h,52h,D8h (Erase) will become one byte longer
and accept 4-bytes address instead of 3-bytes.
This patch provides support for well known instructions in 4-bytes
addressing mode. Also here is the code to enter 4-bytes addressing
mode by execute the instruction B7h (Enter 4-bytes mode).
Patched files
-------------
chipdrivers.h
+ added functions declarations for spi4ba.c
flash.h
+ feature definitions added
Makefile
+ added spi4ba.c
Added files
-----------
spi4ba.h
+ definitions for 4-bytes addressing JEDEC commands
+ functions declarations from spi4ba.c (same as in chipdrivers.h, just to see)
spi4ba.c
+ functions for enter 4-bytes addressing mode
+ functions for read/write/erase in 4-bytes addressing mode
Change-Id: Ie72e2a89cd75fb4d09f48e81c4c1d927c317b7a7
Signed-off-by: Boris Baykov <dev@borisbaykov.com>, Russia, Jan 2014
[clg: ported from
https://www.flashrom.org/pipermail/flashrom/2015-January/013199.html ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-on: https://review.coreboot.org/20513
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Apart from the strange ID (using Sanyo's vendor ID 0x62) the main
difference from the plain SST25WF series is that they lack op codes
0xAD (AAI Word program) and 0x52 (32K erase). The smallest version
does not support dual I/O operations either.
SST25WF080B was tested under Linux with spidev.
Corresponding to flashrom svn r1901.
Tested-by: Ben Gardner <bgardner@wabtec.com>
Signed-off-by: Ben Gardner <bgardner@wabtec.com>
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Since r1833 we added the offset of the virtual register in several
functions, which produced segfaults. This patch renames a few
parameters and reorganizes/fixes various parts of the
changelock_regspace2_block() function - hence the rather big diff.
Thanks to Roman Lebedev for reporting this issue and testing numerous
revisions of this patch.
Corresponding to flashrom svn r1859.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Some Parallel bus chips have a 16-bit mode and an 8-bit mode. They use
normal JEDEC addresses for 16-bit mode and shifted addresses (by 1 bit)
for 8-bit mode. Some programmers can access them in 16-bit mode, but on
all flashrom-supported programmers so far, we access them in 8-bit mode.
This means we have to shift the addresses but apart from the addresses
we can share the code.
This patch makes this possible by checking the chip's FEATURE_ADDR_SHIFTED
flag in common JEDEC functions and applying the right addresses respectively.
Corresponding to flashrom svn r1840.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Tested mainboards:
OK:
- ASUS F2A85-M
Reported by various corebooters
- ASUS M2N-MX SE Plus
Reported by Antonio
- ASUS P5LD2
Reported by François Revol
- Lenovo ThinkPad T530
Reported and partially authored by Edward O'Callaghan
- MSI MS-7502 (Medion MD8833)
Reported by naq on IRC
- Shuttle AB61
Reported by olofolleola4
- ZOTAC IONITX-F-E
Reported by Bernardo Kuri
Flash chips:
- Atmel AT45DB021D to PREW (+PREW)
Reported by The Raven
- Atmel AT25F4096 to PREW (+PREW)
Reported by 공준혁
- GigaDevice GD25Q16(B) to PREW (+PREW)
Reported by luxflow@live.com using a GD25Q16BSIG
- Catalyst CAT28F512
Mark erase and write as known bad (not implemented)
Miscellaneous:
- Various spelling corrections by Daniele Forsi.
- Added and refined a bunch of chips originally investigated by Carl-Daniel.
- Marked the ARM-USB-OCD-H programmer as tested
(reported by Ruud Schramp).
- Tiny other stuff.
Corresponding to flashrom svn r1839.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
29GL chips use a new 3-Byte device ID probing function at addresses
0x01, 0x0E, 0x0F.
Flash chip families supported by this method include...
- EON EN29GL
- Gigadevice GD29GL (if they really exist)
- ISSI (PMC) IS29GL
- Macronix MX29GL (+MX68GL1G0F)
- Spansion S29GL (+S70GL02G)
- Winbond W29GL
This patch adds respective flash chip definitions for chips up to 16 MB from
Eon, ISSI, Macronix and Winbond. Bigger chips as well as those from
Gigadevice and Spansion are left out.
Corresponding to flashrom svn r1835.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
This patch combines two identical block and chip erase functions respectively:
- Merge block_erase_m29f400bt and block_erase_en29lv640b into
erase_block_shifted_jedec.
- Merge block_erase_chip_m29f400bt and block_erase_chip_en29lv640b into
erase_chip_block_shifted_jedec.
Leave their implementations in en29lv640b.c for now.
Corresponding to flashrom svn r1808.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Also, include chipdrivers.h to find conflicting types between exported
declarations and actual implementations.
Corresponding to flashrom svn r1805.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Spi_prettyprint_status_register_default_bpX ->
spi_prettyprint_status_register_bpX_srwd
Why was the default in there anyway? :)
Corresponding to flashrom svn r1802.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
There are two locking strategies used by this umbrella family, one uniform
and one that matches the sector layout of the chip. Refactor the functions
involved and rename the overly complicated file to just stm50.c and the
functions accordingly.
This fixes unlocking of some of the non-uniform chips and gets rid of the
abuse of page_size.
Corresponding to flashrom svn r1736.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
This one is even more strange than the AT45DB chips. Like the AT45DB321C
it does not support any power-of-2 page sizes. There is only one asymmetrical
eraser and that uses two opcodes.
Corresponding to flashrom svn r1725.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
It seems like this model is one-of-a-kind... it shares some properties
with the older versions of the AT45DB series as well as with new ones.
Corresponding to flashrom svn r1724.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Wei Hu
Elyes HAOUAS
Paul Kocialkowski
Nico Huber
Ed Swierk
Boris Baykov
Ben Gardner
Stefan Tauner
Carl-Daniel Hailfinger
Mark Marshall