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This is an attempt at formally distinguishing and supporting the case described in 40795 where an architecture doesn't preserve/restore the complete thread state upon entering/exiting interrupt exception state. This is mainly about promoting the current behavior from the accepted workaround to a formal API specification. This workaround is currently used on ARM64 but RISC-V requires it too. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>