Flavio Ceolin 020df54ba4 xtensa: mmu: Initial implementation ...

Initial support for Xtensa MMU version 3. It is using a two level page
table based on fact that the page table is in the virtual space.  Only
the top level (page directory) is wired mapped in the TLB to avoid
second level page miss.

The mapped memory is completely fragmented in multiple sections, maybe
we find a better way in future.

The exception handler is where we effectively map the memory, the way it
works is:

1) SW try to access some memory address
2) The address is not mapped, so the MMU will try the auto-refill,
   looking the page table
3) The page table contents is not mapped (remember, just the top-level page
   is mapped)
4) An exception will be triggered, in the exception we try to read the
   portion of the page table that maps the original address
5) The address is not mapped, so the MMU will try again the auto-refill.
   This time though, the address is mapped by the top level page that is
   properly mapped. (The top-level page maps the page table itself).

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>

2023-05-23 08:54:29 +02:00

..

xtensa_backtrace.h

…

xtensa_mmu_priv.h

xtensa: mmu: Initial implementation

2023-05-23 08:54:29 +02:00