Every va_start() currently triggers a FPU access trap if FPU is not
already used. This is due to the fact that va_start() must copy FPU
registers that are used for float argument passing into the va_list
object. Flushing the FPU context to its owner and granting access to
the current thread is wasteful if this is only for va_start(),
especially since in most cases there are simply no FP arguments
being passed by the caller.
This is made even worse with exception code (syscalls, IRQ handlers,
etc.) where the exception code has to be resumed with interrupts
disabled upon FPU access as there is no provision for preserving an
interrupted exception mode's FPU context.
Fix those issues by simply simulating the sequence of STR instructions
that the va_start() generates without actually granting FPU access.
We limit ourselves only to exception context to keep changes to a
minimum for now.
This also allows for reverting the ARM64 exception in the nested IRQ
test as it now works properly even if FPU_SHARING is enabled.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
The interrupt offload testcases fail on some boards because the timing
of the delay is too short. Refine the testcases and make it not rely
on the delay timing.
Fixes#35097Fixes#35241
Signed-off-by: Enjia Mai <enjiax.mai@intel.com>
Should not use -1 as an input parameter for unsigned int. Use zero
instead of -1 as invaild interrupt number to fix coverity warning.
Fixes#35146
CID: 235994
Signed-off-by: Enjia Mai <enjiax.mai@intel.com>
Add test cases of direct interrupt for arch x86 and posix.
We register two direct interrupt at build time, then triggering
interrupt and check if ISR handler has executed or not. We also
check irq_enable and irq_disable works.
Why we add an extra compiler option "-mgeneral-regs-only" to make
it works in arch x86. because there might be some existing x87
instructions executing inside interrupt context.
Signed-off-by: Enjia Mai <enjiax.mai@intel.com>
Add test cases of regular interrupt for arch x86. This tests basic
functionailty of IRQ_CONNECT(), irq_enable(), irq_disable(),
irq_lock(), irq_unlock().
Signed-off-by: Enjia Mai <enjiax.mai@intel.com>
Add 3 test cases to test offload job from isr, include:
1. test_isr_offload_job_multiple()
Validate the offloaded work executes immediately or not depends on its
priority, and it offloads to different k_work.
2. test_isr_offload_job_identi()
Validate the offloaded work executes immediately or not depends on its
priority, and it offloads to the identical k_work.
3. test_isr_offload_job()
Use dynamic interrupt instead of irq_offload() to verify the offloaded
work.
Signed-off-by: Enjia Mai <enjiax.mai@intel.com>
This adds FPU sharing support with a lazy context switching algorithm.
Every thread is allowed to use FPU/SIMD registers. In fact, the compiler
may insert FPU reg accesses in anycontext to optimize even non-FP code
unless the -mgeneral-regs-only compiler flag is used, but Zephyr
currently doesn't support such a build.
It is therefore possible to do FP access in IRS as well with this patch
although IRQs are then disabled to prevent nested IRQs in such cases.
Because the thread object grows in size, some tests have to be adjusted.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
The test_prevent_interruption() uses a key for the irq_lock(),
but the key has incorrect data type. This commit makes the key
unsigned int according to API docs.
Fixes#34023
Signed-off-by: Jennifer Williams <jennifer.m.williams@intel.com>
The interrupt_util.h provides utils of trigger irq, now move them into
testsuite. All of the needed test cases can make use of them.
Signed-off-by: Enjia Mai <enjiax.mai@intel.com>
Improve dynamic interrupt test cases of interrupt for platform such as
x86, x86_64, native_posix, this improve code coverage of it.
Signed-off-by: Enjia Mai <enjiax.mai@intel.com>
tests/kernel/interrupt tests interrupt trigger functionality,
however, the Non-Secure Cortex-M mode does not have full control
of the interrupt handling, so this test cannot be guaranteed to
pass when executing in Non-Secure mode. Filter the test out for
Non-Secure Cortex-M builds.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Extend check to determine a usable ARM NVIC IRQ line to verify that the
IRQ line is not always pending.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
GICv3 is now support for SGI generation and test case is updated
to use GICv3 apis. bcm958402m2_a72 can be enabled now.
Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
GICC_BPR has minimum legal values in secure and non-secure states.
'3' is the minimum BPR value leading to group and sub-group priority
as 'gggg.ssss'. In order to make an IRQ preemptible they need to
be in different priority group.
Hence to be generic priority values should be above '0x0f'.
IRQ0 - default priority (low prio)
IRQ1 - 0x0 (highest prio)
Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
... because it is (required).
This makes a difference when building with CMake and forgetting
ZEPHYR_BASE or not registering Zephyr in the CMake package registry.
In this particular case, REQUIRED turns this harmless looking log
statement:
-- Could NOT find Zephyr (missing: Zephyr_DIR)
-- The C compiler identification is GNU 9.3.0
-- The CXX compiler identification is GNU 9.3.0
-- Check for working C compiler: /usr/bin/cc
-- ...
-- ...
-- ...
-- Detecting CXX compile features
-- Detecting CXX compile features - done
CMake Error at CMakeLists.txt:8 (target_sources):
Cannot specify sources for target "app" which is not built by
this project.
... into this louder, clearer, faster and (last but not least) final
error:
CMake Error at CMakeLists.txt:5 (find_package):
Could not find a package configuration file provided by "Zephyr" with
any of the following names:
ZephyrConfig.cmake
zephyr-config.cmake
Add the installation prefix of "Zephyr" to CMAKE_PREFIX_PATH or set
"Zephyr_DIR" to a directory containing one of the above files. If
"Zephyr" provides a separate development package or SDK, be sure it
has been installed.
-- Configuring incomplete, errors occurred!
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
This commit enables nested interrupt test for the Cortex-R platforms
that use the ARM Generic Interrupt Controller (GIC).
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
