This adds support for the TIMER1-4 counter.
Each counter has 24bits and can run on LP_CLK (15-32KHz)
or DIVN clock (32MHz) with prescaler 1-32.
Each counter can have one alarm set.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
This is a new parameter to divide the LPTIM input clock
by a prescaler, changing the max reachable timeout of the LP timer.
It will divide the LPTIM input clock by 1 (reset value) up to 128.
The lptim configuration register is written with a 3bit value.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
- Add Gecko BURTC sys_clock driver to handle wake up from EM2,3 states
- Remove custom PM policy and dependency on HAL sl_power_manager service
- EM1 supported in all configurations
- EM2,3 supported only if SysTick is replaced by BURTC
Signed-off-by: Roman Dobrodii <rdobrodii@antmicro.com>
Modifying counter drivers (rtc and timer) to rely completely on
device tree and not on Kconfig of MDK flags.
Adapting dtsi for all SoCs and adapting test configuration.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Update machine timer drivers to use DT_HAS_<compat>_ENABLED Kconfig symbol
to expose the driver and enable it by default based on NIOSV devicetree.
Signed-off-by: Khor Swee Aun <swee.aun.khor@intel.com>
Align driver with changes introduced in the hal. `nrf_timer_frequency_set`
was changed to `nrf_timer_prescaler_set`, update driver accordingly.
Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Add a st,static-prescaler optional property to DTS
of the stm32 where the LPTIM has a x2 factor on
its clock input.
This property is present or not depending on the stm32.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Fix all line-length errors detected by yamllint:
yamllint -f parsable -c .yamllint $( find -regex '.*\.y[a]*ml' ) | \
grep '(line-length)'
Using a limit is set to 100 columns, not touching the commandlines in
GitHub workflows (at least for now).
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
We are about to add timer reset during driver initialization. First step
is to add 'resets' property, which provides information about reset
register offset and bit.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
NXP S32 System Timer module includes a 32-bit count-up timer and four
32-bit compare channels with a separate interrupt source for each
channel. The timer is driven by the module clock divided by an 8-bit
prescale value.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
DTS property attributes are (by default) not required.
Explicitly specifying `required: false` is redundant.
Perhaps a warning to that effect would be useful.
Signed-off-by: Chris Friedt <cfriedt@meta.com>
Convert timer driver to use a light weight syscon and DTS and convert
register information to use offsets and sys_read/sys_write instead of
structs.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
various microchip bindings set 'girq-cells' and 'pcr-cells'
sections in the bindings. However the bindings where for the
client nodes and thus do not need to set these.
Signed-off-by: Kumar Gala <galak@kernel.org>
