Krystian Hebel e58e532db1 images/regs_module.svg: add missing reset signal ...

Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>

2024-03-14 15:50:05 +01:00

..

dasharo-logo.png

create initial skeleton for documentation

2022-12-28 19:04:10 +01:00

dasharo-logo.png.license

add license, making reuse 3.0 compliant

2024-01-16 23:31:56 +01:00

favicon.png

create initial skeleton for documentation

2022-12-28 19:04:10 +01:00

favicon.png.license

add license, making reuse 3.0 compliant

2024-01-16 23:31:56 +01:00

litedram_core.svg

development/verilog_modules.md: describe additional modules used

2023-11-29 12:36:52 +01:00

litedram_core.svg.license

add license, making reuse 3.0 compliant

2024-01-16 23:31:56 +01:00

lpc_periph.svg

development/verilog_modules.md: describe additional modules used

2023-11-29 12:36:52 +01:00

lpc_periph.svg.license

add license, making reuse 3.0 compliant

2024-01-16 23:31:56 +01:00

neorv32_verilog_wrapper.svg

development/verilog_modules.md: describe additional modules used

2023-11-29 12:36:52 +01:00

neorv32_verilog_wrapper.svg.license

add license, making reuse 3.0 compliant

2024-01-16 23:31:56 +01:00

pinout-2x6-key10-vert.png

tutorials/mainboard-connection.md: add SPI connection instructions

2024-03-12 22:39:30 +01:00

pinout-2x6-key10-vert.png.license

tutorials/mainboard-connection.md: add SPI connection instructions

2024-03-12 22:39:30 +01:00

pinout-2x10-key4-vert.png

tutorials/mainboard-connection.md: add new file

2023-11-27 14:13:47 +01:00

pinout-2x10-key4-vert.png.license

add license, making reuse 3.0 compliant

2024-01-16 23:31:56 +01:00

r512x32.svg

development/verilog_modules.md: describe additional modules used

2023-11-29 12:36:52 +01:00

r512x32.svg.license

add license, making reuse 3.0 compliant

2024-01-16 23:31:56 +01:00

reg-buf-size.png

development/m4_fpga_communication.md: add new document

2023-08-08 22:41:35 +02:00

reg-buf-size.png.license

add license, making reuse 3.0 compliant

2024-01-16 23:31:56 +01:00

reg-locality.png

development/m4_fpga_communication.md: add new document

2023-08-08 22:41:35 +02:00

reg-locality.png.license

add license, making reuse 3.0 compliant

2024-01-16 23:31:56 +01:00

reg-op-type.png

development/m4_fpga_communication.md: add new document

2023-08-08 22:41:35 +02:00

reg-op-type.png.license

add license, making reuse 3.0 compliant

2024-01-16 23:31:56 +01:00

reg-status.png

development/m4_fpga_communication.md: add new document

2023-08-08 22:41:35 +02:00

reg-status.png.license

add license, making reuse 3.0 compliant

2024-01-16 23:31:56 +01:00

regs_module.svg

images/regs_module.svg: add missing reset signal

2024-03-14 15:50:05 +01:00

regs_module.svg.license

add license, making reuse 3.0 compliant

2024-01-16 23:31:56 +01:00

spi_periph.svg

development/verilog_modules.md: add SPI module description

2024-02-14 14:29:05 +01:00

twpm_connection_dev.png

development/testing.md: remove TBDs

2024-01-16 15:10:43 +01:00

twpm_connection_dev.png.license

add license, making reuse 3.0 compliant

2024-01-16 23:31:56 +01:00

twpm_connection.png

development/testing.md: remove TBDs

2024-01-16 15:10:43 +01:00

twpm_connection.png.license

add license, making reuse 3.0 compliant

2024-01-16 23:31:56 +01:00

twpm_top_orangecrab.svg

development/verilog_modules.md: add SPI module description

2024-02-14 14:29:05 +01:00

twpm_top_orangecrab.svg.license

add license, making reuse 3.0 compliant

2024-01-16 23:31:56 +01:00