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79 Commits
Author SHA1 Message Date
Krystian Hebel 2cbf9151b6 roadmap/index.md: update state of phases 
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
 2024-03-15 15:36:52 +01:00
Krystian Hebel cef2e796b9 changelog/index.md: update 
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
 2024-03-14 18:39:13 +01:00
Krystian Hebel e688ed4c1a development/verilog_modules.md: update FPGA utilization numbers 
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
 2024-03-14 18:39:13 +01:00
Krystian Hebel 7006e4ac45 development/testing.md: add test results from VP6670 with SPI TPM 
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
 2024-03-14 17:28:57 +01:00
Krystian Hebel 1388295507 development/verilog_modules.md: add testbench outputs 
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
 2024-03-14 16:12:37 +01:00
Krystian Hebel 68d7ea8227 development/soc_fpga_communication.md: document op_type=0 as error 
This value should never be passed when `exec` is active.

Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
 2024-03-14 15:59:28 +01:00
Krystian Hebel e58e532db1 images/regs_module.svg: add missing reset signal 
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
 2024-03-14 15:50:05 +01:00
Krystian Hebel e80620636f tutorials/mainboard-connection.md: add SPI connection instructions 
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
 2024-03-12 22:39:30 +01:00
Krystian Hebel 37d32d23fc development/verilog_modules.md: add SPI module description 
This also changes description of other modules that were mentioning
LPC module as the only implementation option.

Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
 2024-02-14 14:29:05 +01:00
Krystian Hebel 7b6ea7acc1 development/testing.md: fix link to mainboard connection 
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
 2024-01-18 16:20:34 +01:00
Maciej Pijanowski a28f76aa4a docs/development/testing.md: pre-commit fixes 
Signed-off-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com>
 2024-01-16 23:32:52 +01:00
Maciej Pijanowski 4731d08e12 add license, making reuse 3.0 compliant 
Signed-off-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com>
 2024-01-16 23:31:56 +01:00
Krystian Hebel ac0045fb92 development/testing.md: add missing link, fix issues caught by precommit 
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
 2024-01-16 18:21:17 +01:00
Maciej Pijanowski c2eee630c2 development/testing.md: add more description on connections 
Signed-off-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com>
 2024-01-16 17:15:30 +01:00
Maciej Pijanowski 1540be7ac8 changelog: resolve TBD 
Signed-off-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com>
 2024-01-16 17:15:07 +01:00
Maciej Pijanowski 9431c68704 roadmap: set P6 to done 
Signed-off-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com>
 2024-01-16 15:15:55 +01:00
Maciej Pijanowski 50853d5d24 changelog: add P6 entry 
Signed-off-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com>
 2024-01-16 15:14:33 +01:00
Maciej Pijanowski c5de4cd1e9 development/testing.md: remove TBDs 
Signed-off-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com>
 2024-01-16 15:10:43 +01:00
Maciej Pijanowski d6a0b11ed0 development/testing.md: init 
Signed-off-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com>
 2024-01-16 11:59:31 +01:00
Krystian Hebel 984dea423c development/soc_fpga_communication.md: improve interrupts section 
Interrupts must be masked after a command is received, otherwise IRS
would keep being invoked, which would effectively block any progress
in command execution.

Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
 2023-12-27 17:58:23 +01:00
Krystian Hebel d39a48144c development/verilog_modules.md: fix typo and list of modules external to SoC 
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
 2023-11-29 14:56:03 +01:00
Krystian Hebel 4e20d19bb6 docs/changelog/index.md: add new entry for phase 5 
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
 2023-11-29 12:36:52 +01:00
Krystian Hebel 08270c372b development/verilog_modules.md: describe additional modules used 
This includes:
- Top level
- NEORV32
- LiteDRAM
- TPM RAM

Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
 2023-11-29 12:36:52 +01:00
Krystian Hebel a0eb9ee2ba development/verilog_modules.md: update for current submodule versions 
This only updates existing entries, neither RAM nor NEORV32 are not
added yet.

Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
 2023-11-29 12:36:51 +01:00
Krystian Hebel 8f0f2adc09 development/soc_fpga_communication.md: change for NEORV32 
TwPM implemented for NEORV32 has different address space layout
and way of signaling interrupts.

Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
 2023-11-29 12:36:51 +01:00