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Maurice Ma
93fc6a59a1
Current SBL code used 2MB page table pool size for page table protection. 2MB is too big to be marked as write protected since the it might also contain some other SBL data besides the page table. It caused issue when using LinuxBoot as payload. This patch adjusted the page table pool size to be 4KB, and it fixed the LinuxBoot issue. Signed-off-by: Maurice Ma <maurice.ma@intel.com>
223 lines
7.7 KiB
C
223 lines
7.7 KiB
C
/** @file
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Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PAGING_LIB_H_
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#define _PAGING_LIB_H_
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#define CR0_WP BIT16
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#define IA32_PG_P BIT0
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#define IA32_PG_RW BIT1
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#define IA32_PG_PS BIT7
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#define PAGING_PAE_INDEX_MASK 0x1FF
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#define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull
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#define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull
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#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull
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#define PAGING_L1_ADDRESS_SHIFT 12
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#define PAGING_L2_ADDRESS_SHIFT 21
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#define PAGING_L3_ADDRESS_SHIFT 30
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#define PAGING_L4_ADDRESS_SHIFT 39
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#define PAGE_TABLE_POOL_ALIGNMENT BASE_4KB
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#define PAGE_TABLE_POOL_UNIT_SIZE SIZE_4KB
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#define PAGE_TABLE_POOL_ALIGN_MASK \
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(~(EFI_PHYSICAL_ADDRESS)(PAGE_TABLE_POOL_ALIGNMENT - 1))
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//
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// Page-Map Level-4 Offset (PML4) and
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// Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB
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//
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typedef union {
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struct {
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UINT64 Present:1; // 0 = Not present in memory,
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// 1 = Present in memory
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UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write
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UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User
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UINT64 WriteThrough:1; // 0 = Write-Back caching,
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// 1 = Write-Through caching
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UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached
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UINT64 Accessed:1; // 0 = Not accessed,
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// 1 = Accessed (set by CPU)
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UINT64 Reserved:1; // Reserved
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UINT64 MustBeZero:2; // Must Be Zero
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UINT64 Available:3; // Available for use by system software
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UINT64 PageTableBaseAddress:40; // Page Table Base Address
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UINT64 AvabilableHigh:11; // Available for use by system software
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UINT64 Nx:1; // No Execute bit
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} Bits;
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UINT64 Uint64;
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} PAGE_MAP_AND_DIRECTORY_POINTER;
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//
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// Page Table Entry 2MB
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//
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typedef union {
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struct {
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UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory
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UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write
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UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User
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UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching
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UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached
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UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)
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UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page
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UINT64 MustBe1:1; // Must be 1
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UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
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UINT64 Available:3; // Available for use by system software
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UINT64 PAT:1; //
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UINT64 MustBeZero:8; // Must be zero;
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UINT64 PageTableBaseAddress:31; // Page Table Base Address
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UINT64 AvabilableHigh:11; // Available for use by system software
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UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution
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} Bits;
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UINT64 Uint64;
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} PAGE_TABLE_ENTRY;
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//
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// Page Table Entry 1GB
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//
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typedef union {
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struct {
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UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory
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UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write
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UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User
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UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching
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UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached
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UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)
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UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page
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UINT64 MustBe1:1; // Must be 1
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UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
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UINT64 Available:3; // Available for use by system software
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UINT64 PAT:1; //
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UINT64 MustBeZero:17; // Must be zero;
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UINT64 PageTableBaseAddress:22; // Page Table Base Address
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UINT64 AvabilableHigh:11; // Available for use by system software
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UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution
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} Bits;
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UINT64 Uint64;
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} PAGE_TABLE_1G_ENTRY;
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typedef struct {
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UINT32 Start;
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UINT32 Limit;
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UINT32 Mapping;
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} RANGE;
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/**
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This function returns page tables memory size (2 * SIZE_4KB).
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**/
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UINT32
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EFIAPI
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GetPageTablesMemorySize (
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VOID
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);
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/**
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Allocates and fills in the Page Directory and Page Table Entries to
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establish a 1:1 Virtual to Physical mapping.
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@param [in] Ranges
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@param [in] PageTableMem
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@retval The address of 4 level page map.
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**/
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UINT32
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EFIAPI
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Create4GbPageTablesAndRemapRange (
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IN RANGE Ranges[1],
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IN VOID *PageTableMem
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);
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/**
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ASM inline function Paging32.nasm - Enable Paging
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Set Page Global Enable (Set PGE in CR4)
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loads Pdpe to CR3 and Set PG bit in CR0.
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@param [in] Pdpe pointer to Page Directory and Page Table Entries
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**/
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VOID
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EFIAPI
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EnablePaging32 (
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IN UINT32 *Pdpe
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);
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/**
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ASM inline function Paging32.nasm - Disable Paging (Clear PG bit in CR0).
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**/
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VOID
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EFIAPI
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DisablePaging32 (
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VOID
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);
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/**
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Create 64-bit pagetables, enable long mode and jump to 64-bit entrypoint.
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Enables the 64-bit paging mode on the CPU. CR0, CR3, CR4, and the page tables
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must be properly initialized prior to calling this service. This function
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assumes the current execution mode is 32-bit protected mode with flat
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descriptors. This function is only available on IA-32. After the 64-bit
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paging mode is enabled, control is transferred to the function specified by
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EntryPoint using the new stack specified by NewStack and passing in the
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parameters specified by Context1 and Context2. Context1 and Context2 are
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optional and may be 0. The function EntryPoint must never return.
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If the current execution mode is not 32-bit protected mode with flat
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descriptors, then ASSERT().
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If EntryPoint is 0, then ASSERT().
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If NewStack is 0, then ASSERT().
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@param[in] EntryPoint The 64-bit virtual address of the function to call
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with the new stack after paging is enabled.
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@param[in] Context1 The 64-bit virtual address of the context to pass into
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the EntryPoint function as the first parameter after
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paging is enabled.
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@param[in] Context2 The 64-bit virtual address of the context to pass into
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the EntryPoint function as the second parameter after
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paging is enabled.
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@param[in] NewStack The 64-bit virtual address of the new stack to use for
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the EntryPoint function after paging is enabled.
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**/
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VOID
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EFIAPI
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JumpToLongMode (
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IN UINT64 EntryPoint,
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IN UINT64 Context1, OPTIONAL
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IN UINT64 Context2, OPTIONAL
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IN UINT64 NewStack
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);
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/**
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Whether 64-bit long mode is enabled or not.
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@return TRUE if long mode has already been enabled, otherwise FALSE
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**/
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BOOLEAN
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EFIAPI
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IsLongModeEnabled (
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VOID
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);
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/**
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Whether processor supports 64-bit long mode or not.
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@return TRUE if processor supports 64-bit long mode, otherwise FALSE
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**/
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BOOLEAN
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EFIAPI
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IsLongModeSupported (
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VOID
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);
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#endif
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