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Maurice Ma
8a0a8984f9
EnableAvx ASM is included as part ExtraLibs. Signed-off-by: Maurice Ma <maurice.ma@intel.com> Signed-off-by: Subash Lakkimsetti <subashx.lakkimsetti@intel.com>
48 lines
1.2 KiB
C
48 lines
1.2 KiB
C
/** @file
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Header file for extra base routines
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _EXTRA_BASE_LIB_H_
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#define _EXTRA_BASE_LIB_H_
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/**
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Flush a range of cache lines in the cache coherency domain of the calling
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CPU.
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Flushes the cache lines specified by Address and Length. If Address is not aligned
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on a cache line boundary, then entire cache line containing Address is flushed.
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If Address + Length is not aligned on a cache line boundary, then the entire cache
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line containing Address + Length - 1 is flushed. This function may choose to flush
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the entire cache if that is more efficient than flushing the specified range. If
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Length is 0, the no cache lines are flushed.
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@param[in] Address The base address of the lines to invalidate.
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@param[in] Length The number of bytes to invalidate from the cache.
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**/
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VOID
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EFIAPI
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AsmFlushCacheRange (
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IN VOID *Address,
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IN UINTN Length
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);
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/**
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Enable CPU AVX support if the CPU is capable.
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CPU.
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**/
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VOID
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EFIAPI
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AsmEnableAvx (
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VOID
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);
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#endif
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