Yi Li 6adb9072d5 Let Stage1B run in memory accoss all stages in fast boot mode ...

This will increase time of Board PostMemoryInit hook and TempRamExit,
but improve the performance of PostTempRamExit hook, PreSiliconInit hook
and FSP-S.

In total, the boot time can be reduced by ~20ms.

Signed-off-by: Yi Li <yi1.li@intel.com>

2024-04-02 09:45:30 -07:00

..

Include

fix: [MTL] Add IgdOpRegionDefine 3.0 header (#2017)

2023-09-05 18:17:28 -04:00

IncludePrivate

[EHL] Revert the WA for POSC issue Pt2

2022-01-13 08:11:10 -08:00

Library

Let Stage1B run in memory accoss all stages in fast boot mode

2024-04-02 09:45:30 -07:00

PcdData

Use LF line endings in the repository

2021-11-10 12:46:42 -08:00

Stage1A

Move TCO timer start and TCO status check to SG1B

2022-12-02 12:50:59 -07:00

Stage1B

Revert "fix: [TPM] correcting cfg data and key hash" (#2122)

2024-01-23 22:46:55 -07:00

Stage2

feat: Validate BMP headers to protect against LogoFAIL.

2024-01-08 15:04:47 -07:00

Tools

feat: creating actm binary to be copied in build folder (#2141)

2024-03-21 21:21:13 -07:00

BootloaderCorePkg.dec

feat: creating actm binary to be copied in build folder (#2141)

2024-03-21 21:21:13 -07:00

BootloaderCorePkg.dsc

feat: creating actm binary to be copied in build folder (#2141)

2024-03-21 21:21:13 -07:00

BootloaderCorePkg.fdf

Use LF line endings in the repository

2021-11-10 12:46:42 -08:00