Vincent Chen f74c113997 FWU: Adjust the starting offset of BIOS payload in capsule ...

When firmware update is processing BIOS payload, it will
locate Stage1A FV and get SBL version file for verification.
The files in FV are expected to be located at 8-byte aligned
offset. There is chance to break the alignment when a payload
of variable size, e.g. CMDI file, is packed in front of BIOS
payload. So this patch adjusts the starting offset of BIOS
payload to be 8-byte aligned with 0xFF paddings.

Signed-off-by: Vincent Chen <vincent.chen@intel.com>

2022-07-15 16:02:03 -07:00

..

Include

Add MP service for payload

2022-03-02 09:04:08 -08:00

IncludePrivate

[EHL] Revert the WA for POSC issue Pt2

2022-01-13 08:11:10 -08:00

Library

[Common][EHL] Adding SMBIOS Type3

2022-06-27 10:47:05 -07:00

PcdData

Use LF line endings in the repository

2021-11-10 12:46:42 -08:00

Stage1A

Add CPU signature and ucode revision print

2022-03-01 12:36:55 -08:00

Stage1B

Use LF line endings in the repository

2021-11-10 12:46:42 -08:00

Stage2

Add support for getting csme boot time perf data

2022-05-11 09:02:52 -07:00

Tools

FWU: Adjust the starting offset of BIOS payload in capsule

2022-07-15 16:02:03 -07:00

BootloaderCorePkg.dec

Support different CPU sort method

2022-04-14 10:23:27 -07:00

BootloaderCorePkg.dsc

Leverage EDKII Build System to Perform uCode Slotting

2022-05-19 09:56:34 -07:00

BootloaderCorePkg.fdf

Use LF line endings in the repository

2021-11-10 12:46:42 -08:00