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Maurice Ma
85 lines
1.9 KiB
C
85 lines
1.9 KiB
C
/** @file
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php.
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef _PAGING_LIB_H_
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#define _PAGING_LIB_H_
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typedef struct {
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UINT32 Start;
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UINT32 Limit;
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UINT32 Mapping;
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} RANGE;
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/**
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This function returns page tables memory size (2 * SIZE_4KB).
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**/
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UINT32
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EFIAPI
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GetPageTablesMemorySize (
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VOID
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);
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/**
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Allocates and fills in the Page Directory and Page Table Entries to
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establish a 1:1 Virtual to Physical mapping.
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@param [in] Ranges
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@param [in] PageTableMem
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@retval The address of 4 level page map.
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**/
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UINT32
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EFIAPI
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Create4GbPageTablesAndRemapRange (
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IN RANGE Ranges[1],
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IN VOID *PageTableMem
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);
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/**
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ASM inline function Paging32.nasm - Enable Paging
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Set Page Global Enable (Set PGE in CR4)
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loads Pdpe to CR3 and Set PG bit in CR0.
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@param [in] Pdpe pointer to Page Directory and Page Table Entries
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**/
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VOID
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EFIAPI
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EnablePaging32 (
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IN UINT32 *Pdpe
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);
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/**
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ASM inline function Paging32.nasm - Disable Paging (Clear PG bit in CR0).
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**/
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VOID
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EFIAPI
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DisablePaging32 (
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VOID
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);
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/**
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ASM inline function Paging32.nasm
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@param [in] StartAddress Pointer to Start address where cache needs to be flushed
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@param [in] EndAddress Pointer to End address where cache needs to be flushed
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**/
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VOID *
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EFIAPI
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FlushCacheLine (
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IN VOID *StartAddress,
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IN VOID *EndAddress
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);
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#endif
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