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Maurice Ma
3b457679ec
Current SBL has platform specific GetBuiltInConfigData() implementation because the internal CFGDATA blob is embedded into Stage1B data section. Instead, it can be put into Stage1B FV FFS file, and then use a PCD to get the base. In this way, it can be handled directly in core code and remove platform specific implementation. Signed-off-by: Maurice Ma <maurice.ma@intel.com>
282 lines
8.3 KiB
Plaintext
Executable File
282 lines
8.3 KiB
Plaintext
Executable File
## @file
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# FDF file of Platform.
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#
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# Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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#
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##
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[Defines]
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DEFINE FLASH_ERASE_POLARITY = 1
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DEFINE FV_DIR = $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/FV
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DEFINE IA_DIR = $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/IA32
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#------------------------------------------------------------------------------
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# STAGE1A FD
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# STAGE1A_FD_BASE, STAGE1A_FD_SIZE, STAGE1A_FD_NUMBLK
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#------------------------------------------------------------------------------
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[FD.STAGE1A]
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BaseAddress = $(STAGE1A_FD_BASE)
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Size = $(STAGE1A_FD_SIZE)
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BlockSize = $(FLASH_BLOCK_SIZE)
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NumBlocks = $(STAGE1A_FD_NUMBLK)
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ErasePolarity = $(FLASH_ERASE_POLARITY)
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!if $(FSP_T_SIZE) > 0
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$(FSP_T_OFFSET) | $(FSP_T_SIZE)
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FILE = $(FV_DIR)/FSP_T.bin
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!endif
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$(STAGE1A_FV_OFFSET) | $(STAGE1A_FV_SIZE)
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FV = STAGE1A
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#------------------------------------------------------------------------------
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# STAGE1B FD
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# STAGE1B_FD_BASE, STAGE1B_FD_SIZE, STAGE1B_FD_NUMBLK
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#------------------------------------------------------------------------------
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[FD.STAGE1B]
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BaseAddress = $(STAGE1B_FD_BASE)
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Size = $(STAGE1B_FD_SIZE)
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BlockSize = $(FLASH_BLOCK_SIZE)
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NumBlocks = $(STAGE1B_FD_NUMBLK)
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ErasePolarity = $(FLASH_ERASE_POLARITY)
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$(STAGE1B_FV_OFFSET) | $(STAGE1B_FV_SIZE)
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FV = STAGE1B
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!if $(FSP_M_SIZE) > 0
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$(FSP_M_OFFSET) | $(FSP_M_SIZE)
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FILE = $(FV_DIR)/FSP_M.bin
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!endif
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#------------------------------------------------------------------------------
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# STAGE2 FD
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#------------------------------------------------------------------------------
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[FD.STAGE2]
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BaseAddress = $(STAGE2_FD_BASE)
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Size = $(STAGE2_FD_SIZE)
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BlockSize = $(FLASH_BLOCK_SIZE)
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NumBlocks = $(STAGE2_FD_NUMBLK)
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ErasePolarity = $(FLASH_ERASE_POLARITY)
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$(STAGE2_FV_OFFSET) | $(STAGE2_FV_SIZE)
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FV = STAGE2
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!if $(FSP_S_SIZE) > 0
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$(FSP_S_OFFSET) | $(FSP_S_SIZE)
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FILE = $(FV_DIR)/FSP_S.bin
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!endif
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#------------------------------------------------------------------------------
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# OsLoader FD
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#------------------------------------------------------------------------------
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[FD.OsLoader]
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BaseAddress = $(PAYLOAD_EXE_BASE)
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Size = $(OS_LOADER_FD_SIZE)
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BlockSize = $(FLASH_BLOCK_SIZE)
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NumBlocks = $(OS_LOADER_FD_NUMBLK)
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ErasePolarity = $(FLASH_ERASE_POLARITY)
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0x00000000 | $(OS_LOADER_FD_SIZE)
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FV = OsLoader
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#------------------------------------------------------------------------------
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# STAGE1A FV
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#------------------------------------------------------------------------------
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[FV.STAGE1A]
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BlockSize = $(FLASH_BLOCK_SIZE)
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FvAlignment = 16
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ERASE_POLARITY = 1
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MEMORY_MAPPED = TRUE
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STICKY_WRITE = TRUE
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LOCK_CAP = TRUE
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LOCK_STATUS = TRUE
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WRITE_DISABLED_CAP = TRUE
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WRITE_ENABLED_CAP = TRUE
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WRITE_STATUS = TRUE
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WRITE_LOCK_CAP = TRUE
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WRITE_LOCK_STATUS = TRUE
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READ_DISABLED_CAP = TRUE
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READ_ENABLED_CAP = TRUE
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READ_STATUS = TRUE
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READ_LOCK_CAP = TRUE
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READ_LOCK_STATUS = TRUE
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FILE RAW = 3473A022-C3C2-4964-B309-22B3DFB0B6CA {
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SECTION RAW = $(FV_DIR)/VerInfo.bin
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}
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FILE RAW = 3CEA8EF3-95FC-476F-ABA5-7EC5DFA1D77B {
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SECTION RAW = $(FV_DIR)/FlashMap.bin
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}
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!if $(HAVE_FIT_TABLE)
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FILE RAW = CD17FF5E-7731-4d16-8441-FC7A113C392F {
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SECTION RAW = $(FV_DIR)/FitTable.bin
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}
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!endif
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!if $(HAVE_VERIFIED_BOOT)
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FILE RAW = 18EDB1DF-1DBE-4EC5-8E26-C44808B546E1 {
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SECTION RAW = $(FV_DIR)/HashStore.bin
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}
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!endif
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FILE RAW = EFAC3859-B680-4232-A159-F886F2AE0B83 {
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SECTION RAW = $(IA_DIR)/BootloaderCorePkg/PcdData/PcdData/OUTPUT/PEIPcdDataBase.raw
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}
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INF $(PLATFORM_PACKAGE)/Stage1A/Stage1A.inf
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INF RuleOverride = RESET_VECTOR USE = IA32 $(PLATFORM_PACKAGE)/Stage1A/Ia32/Vtf0/Bin/ResetVector.inf
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#------------------------------------------------------------------------------
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# STAGE1B FV
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#------------------------------------------------------------------------------
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[FV.STAGE1B]
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FvForceRebase = TRUE
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BlockSize = $(FLASH_BLOCK_SIZE)
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FvAlignment = 16
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ERASE_POLARITY = 1
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MEMORY_MAPPED = TRUE
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STICKY_WRITE = TRUE
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LOCK_CAP = TRUE
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LOCK_STATUS = TRUE
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WRITE_DISABLED_CAP = TRUE
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WRITE_ENABLED_CAP = TRUE
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WRITE_STATUS = TRUE
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WRITE_LOCK_CAP = TRUE
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WRITE_LOCK_STATUS = TRUE
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READ_DISABLED_CAP = TRUE
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READ_ENABLED_CAP = TRUE
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READ_STATUS = TRUE
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READ_LOCK_CAP = TRUE
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READ_LOCK_STATUS = TRUE
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INF $(PLATFORM_PACKAGE)/Stage1B/Stage1B.inf
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FILE FREEFORM = 016E6CD0-4834-4C7E-BCFE-41DFB88A6A6D {
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SECTION RAW = $(FV_DIR)/CfgDataInt.bin
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}
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#------------------------------------------------------------------------------
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# STAGE2 FV
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#------------------------------------------------------------------------------
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[FV.STAGE2]
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BlockSize = $(FLASH_BLOCK_SIZE)
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FvAlignment = 16
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ERASE_POLARITY = 1
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MEMORY_MAPPED = TRUE
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STICKY_WRITE = TRUE
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LOCK_CAP = TRUE
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LOCK_STATUS = TRUE
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WRITE_DISABLED_CAP = TRUE
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WRITE_ENABLED_CAP = TRUE
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WRITE_STATUS = TRUE
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WRITE_LOCK_CAP = TRUE
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WRITE_LOCK_STATUS = TRUE
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READ_DISABLED_CAP = TRUE
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READ_ENABLED_CAP = TRUE
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READ_STATUS = TRUE
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READ_LOCK_CAP = TRUE
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READ_LOCK_STATUS = TRUE
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INF $(PLATFORM_PACKAGE)/Stage2/Stage2.inf
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!if $(HAVE_ACPI_TABLE)
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INF RuleOverride = ACPITABLE Platform/$(BOARD_PKG_NAME)/AcpiTables/AcpiTables.inf
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!endif
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!if $(HAVE_VBT_BIN)
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FILE FREEFORM = E08CA6D5-8D02-43ae-ABB1-952CC787C933 {
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SECTION RAW = $(FV_DIR)/Vbt.bin
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}
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!endif
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!if $(ENABLE_SPLASH)
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FILE FREEFORM = 5E2D3BE9-AD72-4D1D-AAD5-6B08AF921590 {
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SECTION RAW = $(LOGO_FILE)
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}
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!endif
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#------------------------------------------------------------------------------
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# OS Loader Payload as an FV
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#------------------------------------------------------------------------------
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[FV.OsLoader]
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BlockSize = $(FLASH_BLOCK_SIZE)
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FvAlignment = 16
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ERASE_POLARITY = 1
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MEMORY_MAPPED = TRUE
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STICKY_WRITE = TRUE
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LOCK_CAP = TRUE
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LOCK_STATUS = TRUE
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WRITE_DISABLED_CAP = TRUE
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WRITE_ENABLED_CAP = TRUE
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WRITE_STATUS = TRUE
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WRITE_LOCK_CAP = TRUE
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WRITE_LOCK_STATUS = TRUE
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READ_DISABLED_CAP = TRUE
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READ_ENABLED_CAP = TRUE
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READ_STATUS = TRUE
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READ_LOCK_CAP = TRUE
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READ_LOCK_STATUS = TRUE
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INF PayloadPkg/OsLoader/OsLoader.inf
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#------------------------------------------------------------------------------
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# FwUpdate FV to make FirmwareUpdate.efi visible to modules
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#------------------------------------------------------------------------------
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[FV.FwUpdate]
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BlockSize = $(FLASH_BLOCK_SIZE)
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FvAlignment = 16
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ERASE_POLARITY = 1
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MEMORY_MAPPED = TRUE
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STICKY_WRITE = TRUE
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LOCK_CAP = TRUE
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LOCK_STATUS = TRUE
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WRITE_DISABLED_CAP = TRUE
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WRITE_ENABLED_CAP = TRUE
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WRITE_STATUS = TRUE
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WRITE_LOCK_CAP = TRUE
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WRITE_LOCK_STATUS = TRUE
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READ_DISABLED_CAP = TRUE
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READ_ENABLED_CAP = TRUE
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READ_STATUS = TRUE
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READ_LOCK_CAP = TRUE
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READ_LOCK_STATUS = TRUE
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!if $(ENABLE_FWU)
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INF PayloadPkg/FirmwareUpdate/FirmwareUpdate.inf
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!endif
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################################################################################
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#
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# Rules are use with the [FV] section's module INF type to define
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# how an FFS file is created for a given INF file. The following Rule are the default
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# rules for the different module type. User can add the customized rules to define the
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# content of the FFS file.
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#
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################################################################################
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[Rule.Common.PEIM]
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FILE PEIM = $(NAMED_GUID) {
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TE TE Align=16 $(INF_OUTPUT)/$(MODULE_NAME).efi
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}
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[Rule.Common.SEC.RESET_VECTOR]
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FILE RAW = $(NAMED_GUID) {
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RAW RAW |.raw
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}
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[Rule.Common.USER_DEFINED.RAWBIN]
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FILE RAW = $(NAMED_GUID) {
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RAW BIN |.acpi
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}
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[Rule.Common.USER_DEFINED.ACPITABLE]
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FILE FREEFORM = $(NAMED_GUID) {
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RAW ACPI Optional |.acpi
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RAW ASL Optional |.aml
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}
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