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Before this change, whenever SG02 is corrupted in both BP0 and BP1, SBL will continuously loop trying to recover BP0 via BP1 and vice versa This change makes it so that, if a failure is detected on a recovery flow, the CPU halts Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
44 lines
766 B
C
44 lines
766 B
C
/** @file
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The header file for firmware resiliency definitions.
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Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _FIRMWARE_RESILIENCY_LIB_H_
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#define _FIRMWARE_RESILIENCY_LIB_H_
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/**
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Retrieve FW update state from the reserved region
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@retval StateMachine The current FWU state machine
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**/
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UINT8
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EFIAPI
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GetFwuStateMachine (
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VOID
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);
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/**
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Check if ACM detected corruption in IBB
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**/
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VOID
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EFIAPI
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CheckForAcmFailures (
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VOID
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);
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/**
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Check if TCO timer detected corruption in OBB or a dead loop/crash in IBB/OBB
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@param[in] BootFailureThreshold The number of boots to attempt before recovery
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**/
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VOID
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EFIAPI
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CheckForTcoTimerFailures (
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IN UINT8 BootFailureThreshold
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);
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#endif
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