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Convert the line endings stored for all text files in the repository to LF. The majority previously used DOS-style CRLF line endings. Add a .gitattributes file to enforce this and treat certain extensions as never being text files. Update PatchCheck.py to insist on LF line endings rather than CRLF. However, its other checks fail on this commit due to lots of pre-existing complaints that it only notices because the line endings have changed. Silicon/QemuSocPkg/FspBin/Patches/0001-Build-QEMU-FSP-2.0-binaries.patch needs to be treated as binary since it contains a mixture of line endings. This change has implications depending on the client platform you are using the repository from: * Windows The usual configuration for Git on Windows means that text files will be checked out to the work tree with DOS-style CRLF line endings. If that's not the case then you can configure Git to do so for the entire machine with: git config --global core.autocrlf true or for just the repository with: git config core.autocrlf true Line endings will be normalised to LF when they are committed to the repository. If you commit a text file with only LF line endings then it will be converted to CRLF line endings in your work tree. * Linux, MacOS and other Unices The usual configuration for Git on such platforms is to check files out of the repository with LF line endings. This is probably the right thing for you. In the unlikely even that you are using Git on Unix but editing or compiling on Windows for some reason then you may need to tweak your configuration to force the use of CRLF line endings as described above. * General For more information see https://docs.github.com/en/get-started/getting-started-with-git/configuring-git-to-handle-line-endings . Fixes: https://github.com/slimbootloader/slimbootloader/issues/1400 Signed-off-by: Mike Crowe <mac@mcrowe.com>
117 lines
3.4 KiB
C
117 lines
3.4 KiB
C
/** @file
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Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef __USB_DEVICE_DXE_H__
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#define __USB_DEVICE_DXE_H__
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#include <PiPei.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/PcdLib.h>
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#include <Library/IoLib.h>
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#include <Protocol/EfiUsbFnIo.h>
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#include <Protocol/UsbDeviceModeProtocol.h>
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#include "UsbFuncIo.h"
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#include "UsbDeviceMode.h"
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#define PCI_IF_USBDEV 0xFE
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#define EFI_USB_DEV_SIGNATURE 0x55534244 //"USBD"
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#define USBFUIO_CONTEXT_FROM_PROTOCOL(a) CR (a, USB_XDCI_DEV_CONTEXT, UsbFunIoProtocol, EFI_USB_DEV_SIGNATURE)
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#define USBUSBD_CONTEXT_FROM_PROTOCOL(a) CR (a, USB_XDCI_DEV_CONTEXT, UsbDevModeProtocol, EFI_USB_DEV_SIGNATURE)
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typedef struct _USB_FUIO_EVENT_NODE USB_FUIO_EVENT_NODE;
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#pragma pack(1)
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struct _USB_FUIO_EVENT_NODE {
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EFI_USBFN_MESSAGE Message;
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UINTN PayloadSize;
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EFI_USBFN_MESSAGE_PAYLOAD Payload;
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USB_FUIO_EVENT_NODE *Nextptr;
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};
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typedef struct {
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UINTN Signature;
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UINTN XdciMmioBarAddr;
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EFI_HANDLE XdciHandle;
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//
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// Timer to handle EndPoint event periodically.
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//
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EFI_EVENT XdciPollTimer;
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EFI_USB_DEVICE_MODE_PROTOCOL UsbDevModeProtocol;
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EFI_USBFN_IO_PROTOCOL UsbFunIoProtocol;
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//
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// Structure members used by UsbFunIoProtocol.
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//
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USB_MEM_NODE *FirstNodePtr;
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EFI_USB_DEVICE_INFO *DevInfoPtr;
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EFI_USB_CONFIG_INFO IndexPtrConfig;
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EFI_USB_INTERFACE_INFO IndexPtrInteface;
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USB_DEVICE_ENDPOINT_INFO IndexPtrInEp;
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USB_DEVICE_ENDPOINT_INFO IndexPtrOutEp;
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XDCI_CORE_HANDLE *XdciDrvIfHandle;
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USB_DEV_CORE *DrvCore;
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UINT16 VendorId;
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UINT16 DeviceId;
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USBD_EP_XFER_REC EndPointXferRec[DWC_XDCI_MAX_ENDPOINTS];
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BOOLEAN StartUpController;
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BOOLEAN DevReConnect;
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BOOLEAN DevResetFlag;
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EFI_EVENT TimerEvent;
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USB_FUIO_EVENT_NODE *EventNodePtr;
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//
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// Following structure members are used by UsbDevModeProtocol.
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//
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} USB_XDCI_DEV_CONTEXT;
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#pragma pack()
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EFI_STATUS
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EFIAPI
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GetUsbPortType (
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EFI_USBFN_PORT_TYPE *PortType
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);
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VOID
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EFIAPI
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PlatformSpecificInit (
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VOID
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);
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#if 0
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extern EFI_COMPONENT_NAME_PROTOCOL mUsbDeviceDxeComponentName;
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extern EFI_COMPONENT_NAME2_PROTOCOL mUsbDeviceDxeComponentName2;
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#endif
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extern USB_XDCI_DEV_CONTEXT *mUsbXdciDevContext;
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extern USB_DEVICE_PLATFORM_INFO mUsbDeviceInfo;
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#define MmPciAddress( Segment, Bus, Device, Function, Register ) \
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( (UINTN)PcdGet64(PcdPciExpressBaseAddress) + \
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(UINTN)(Bus << 20) + \
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(UINTN)(Device << 15) + \
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(UINTN)(Function << 12) + \
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(UINTN)(Register) \
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)
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///
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/// xHCI MMIO registers
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///
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#define R_XHCI_MEM_DUAL_ROLE_CFG0 0x80D8
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#define B_XHCI_EN_PIPE4_SYNC BIT30 ///< enable/disable PIPE 4.1 synchronous phystatus
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#define R_XHCI_MEM_DUAL_ROLE_CFG1 0x80DC
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#define R_XHCI_MEM_BASE 0x10 ///< Memory Base Address
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#define B_XHCI_MEM_BASE_BA 0xFFFFFFFFFFFF0000 ///< Base Address
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#define R_OTG_BAR0 0x10 ///< BAR 0
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#define B_OTG_BAR0_BA 0xFFE00000 ///< Base Address
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#endif
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