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458 lines
11 KiB
C
458 lines
11 KiB
C
/** @file
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Public include file for Local APIC library.
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Local APIC library assumes local APIC is enabled. It does not
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handles cases where local APIC is disabled.
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Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef __LOCAL_APIC_LIB_H__
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#define __LOCAL_APIC_LIB_H__
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#define LOCAL_APIC_MODE_XAPIC 0x1 ///< xAPIC mode.
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#define LOCAL_APIC_MODE_X2APIC 0x2 ///< x2APIC mode.
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/**
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Retrieve the base address of local APIC.
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@return The base address of local APIC.
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**/
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UINTN
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EFIAPI
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GetLocalApicBaseAddress (
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VOID
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);
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/**
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Set the base address of local APIC.
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If BaseAddress is not aligned on a 4KB boundary, then ASSERT().
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@param[in] BaseAddress Local APIC base address to be set.
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**/
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VOID
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EFIAPI
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SetLocalApicBaseAddress (
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IN UINTN BaseAddress
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);
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/**
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Get the current local APIC mode.
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If local APIC is disabled, then ASSERT.
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@retval LOCAL_APIC_MODE_XAPIC current APIC mode is xAPIC.
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@retval LOCAL_APIC_MODE_X2APIC current APIC mode is x2APIC.
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**/
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UINTN
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EFIAPI
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GetApicMode (
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VOID
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);
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/**
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Set the current local APIC mode.
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If the specified local APIC mode is not valid, then ASSERT.
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If the specified local APIC mode can't be set as current, then ASSERT.
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@param ApicMode APIC mode to be set.
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@note This API must not be called from an interrupt handler or SMI handler.
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It may result in unpredictable behavior.
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**/
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VOID
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EFIAPI
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SetApicMode (
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IN UINTN ApicMode
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);
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/**
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Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.
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In xAPIC mode, the initial local APIC ID may be different from current APIC ID.
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In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case,
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the 32-bit local APIC ID is returned as initial APIC ID.
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@return 32-bit initial local APIC ID of the executing processor.
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**/
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UINT32
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EFIAPI
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GetInitialApicId (
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VOID
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);
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/**
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Get the local APIC ID of the executing processor.
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@return 32-bit local APIC ID of the executing processor.
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**/
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UINT32
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EFIAPI
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GetApicId (
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VOID
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);
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/**
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Get the value of the local APIC version register.
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@return the value of the local APIC version register.
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**/
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UINT32
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EFIAPI
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GetApicVersion (
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VOID
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);
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/**
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Send a Fixed IPI to a specified target processor.
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This function returns after the IPI has been accepted by the target processor.
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@param ApicId The local APIC ID of the target processor.
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@param Vector The vector number of the interrupt being sent.
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**/
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VOID
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EFIAPI
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SendFixedIpi (
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IN UINT32 ApicId,
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IN UINT8 Vector
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);
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/**
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Send a Fixed IPI to all processors excluding self.
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This function returns after the IPI has been accepted by the target processors.
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@param Vector The vector number of the interrupt being sent.
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**/
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VOID
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EFIAPI
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SendFixedIpiAllExcludingSelf (
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IN UINT8 Vector
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);
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/**
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Send a SMI IPI to a specified target processor.
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This function returns after the IPI has been accepted by the target processor.
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@param ApicId Specify the local APIC ID of the target processor.
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**/
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VOID
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EFIAPI
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SendSmiIpi (
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IN UINT32 ApicId
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);
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/**
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Send a SMI IPI to all processors excluding self.
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This function returns after the IPI has been accepted by the target processors.
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**/
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VOID
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EFIAPI
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SendSmiIpiAllExcludingSelf (
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VOID
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);
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/**
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Send an INIT IPI to a specified target processor.
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This function returns after the IPI has been accepted by the target processor.
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@param ApicId Specify the local APIC ID of the target processor.
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**/
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VOID
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EFIAPI
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SendInitIpi (
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IN UINT32 ApicId
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);
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/**
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Send an INIT IPI to all processors excluding self.
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This function returns after the IPI has been accepted by the target processors.
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**/
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VOID
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EFIAPI
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SendInitIpiAllExcludingSelf (
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VOID
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);
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/**
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Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.
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This function returns after the IPI has been accepted by the target processor.
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if StartupRoutine >= 1M, then ASSERT.
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if StartupRoutine is not multiple of 4K, then ASSERT.
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@param ApicId Specify the local APIC ID of the target processor.
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@param StartupRoutine Points to a start-up routine which is below 1M physical
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address and 4K aligned.
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**/
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VOID
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EFIAPI
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SendInitSipiSipi (
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IN UINT32 ApicId,
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IN UINT32 StartupRoutine
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);
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/**
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Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.
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This function returns after the IPI has been accepted by the target processors.
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if StartupRoutine >= 1M, then ASSERT.
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if StartupRoutine is not multiple of 4K, then ASSERT.
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@param StartupRoutine Points to a start-up routine which is below 1M physical
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address and 4K aligned.
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**/
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VOID
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EFIAPI
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SendInitSipiSipiAllExcludingSelf (
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IN UINT32 StartupRoutine
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);
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/**
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Initialize the state of the SoftwareEnable bit in the Local APIC
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Spurious Interrupt Vector register.
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@param Enable If TRUE, then set SoftwareEnable to 1
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If FALSE, then set SoftwareEnable to 0.
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**/
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VOID
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EFIAPI
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InitializeLocalApicSoftwareEnable (
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IN BOOLEAN Enable
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);
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/**
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Programming Virtual Wire Mode.
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This function programs the local APIC for virtual wire mode following
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the example described in chapter A.3 of the MP 1.4 spec.
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IOxAPIC is not involved in this type of virtual wire mode.
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**/
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VOID
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EFIAPI
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ProgramVirtualWireMode (
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VOID
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);
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/**
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Disable LINT0 & LINT1 interrupts.
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This function sets the mask flag in the LVT LINT0 & LINT1 registers.
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**/
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VOID
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EFIAPI
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DisableLvtInterrupts (
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VOID
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);
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/**
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Read the initial count value from the init-count register.
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@return The initial count value read from the init-count register.
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**/
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UINT32
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EFIAPI
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GetApicTimerInitCount (
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VOID
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);
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/**
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Read the current count value from the current-count register.
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@return The current count value read from the current-count register.
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**/
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UINT32
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EFIAPI
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GetApicTimerCurrentCount (
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VOID
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);
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/**
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Initialize the local APIC timer.
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The local APIC timer is initialized and enabled.
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@param DivideValue The divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.
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If it is 0, then use the current divide value in the DCR.
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@param InitCount The initial count value.
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@param PeriodicMode If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.
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@param Vector The timer interrupt vector number.
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**/
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VOID
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EFIAPI
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InitializeApicTimer (
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IN UINTN DivideValue,
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IN UINT32 InitCount,
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IN BOOLEAN PeriodicMode,
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IN UINT8 Vector
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);
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/**
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Get the state of the local APIC timer.
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@param DivideValue Return the divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.
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@param PeriodicMode Return the timer mode. If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.
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@param Vector Return the timer interrupt vector number.
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**/
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VOID
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EFIAPI
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GetApicTimerState (
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OUT UINTN *DivideValue OPTIONAL,
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OUT BOOLEAN *PeriodicMode OPTIONAL,
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OUT UINT8 *Vector OPTIONAL
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);
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/**
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Enable the local APIC timer interrupt.
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**/
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VOID
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EFIAPI
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EnableApicTimerInterrupt (
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VOID
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);
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/**
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Disable the local APIC timer interrupt.
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**/
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VOID
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EFIAPI
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DisableApicTimerInterrupt (
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VOID
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);
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/**
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Get the local APIC timer interrupt state.
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@retval TRUE The local APIC timer interrupt is enabled.
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@retval FALSE The local APIC timer interrupt is disabled.
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**/
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BOOLEAN
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EFIAPI
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GetApicTimerInterruptState (
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VOID
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);
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/**
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Send EOI to the local APIC.
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**/
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VOID
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EFIAPI
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SendApicEoi (
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VOID
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);
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/**
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Get the 32-bit address that a device should use to send a Message Signaled
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Interrupt (MSI) to the Local APIC of the currently executing processor.
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@return 32-bit address used to send an MSI to the Local APIC.
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**/
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UINT32
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EFIAPI
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GetApicMsiAddress (
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VOID
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);
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/**
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Get the 64-bit data value that a device should use to send a Message Signaled
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Interrupt (MSI) to the Local APIC of the currently executing processor.
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If Vector is not in range 0x10..0xFE, then ASSERT().
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If DeliveryMode is not supported, then ASSERT().
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@param Vector The 8-bit interrupt vector associated with the MSI.
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Must be in the range 0x10..0xFE
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@param DeliveryMode A 3-bit value that specifies how the recept of the MSI
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is handled. The only supported values are:
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0: LOCAL_APIC_DELIVERY_MODE_FIXED
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1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY
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2: LOCAL_APIC_DELIVERY_MODE_SMI
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4: LOCAL_APIC_DELIVERY_MODE_NMI
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5: LOCAL_APIC_DELIVERY_MODE_INIT
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7: LOCAL_APIC_DELIVERY_MODE_EXTINT
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@param LevelTriggered TRUE specifies a level triggered interrupt.
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FALSE specifies an edge triggered interrupt.
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@param AssertionLevel Ignored if LevelTriggered is FALSE.
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TRUE specifies a level triggered interrupt that active
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when the interrupt line is asserted.
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FALSE specifies a level triggered interrupt that active
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when the interrupt line is deasserted.
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@return 64-bit data value used to send an MSI to the Local APIC.
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**/
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UINT64
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EFIAPI
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GetApicMsiValue (
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IN UINT8 Vector,
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IN UINTN DeliveryMode,
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IN BOOLEAN LevelTriggered,
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IN BOOLEAN AssertionLevel
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);
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/**
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Get Package ID/Core ID/Thread ID of a processor.
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The algorithm assumes the target system has symmetry across physical
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package boundaries with respect to the number of logical processors
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per package, number of cores per package.
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@param[in] InitialApicId Initial APIC ID of the target logical processor.
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@param[out] Package Returns the processor package ID.
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@param[out] Core Returns the processor core ID.
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@param[out] Thread Returns the processor thread ID.
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**/
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VOID
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EFIAPI
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GetProcessorLocationByApicId (
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IN UINT32 InitialApicId,
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OUT UINT32 *Package OPTIONAL,
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OUT UINT32 *Core OPTIONAL,
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OUT UINT32 *Thread OPTIONAL
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);
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/**
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Get Package ID/Module ID/Tile ID/Die ID/Core ID/Thread ID of a processor.
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The algorithm assumes the target system has symmetry across physical
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package boundaries with respect to the number of threads per core, number of
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cores per module, number of modules per tile, number of tiles per die, number
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of dies per package.
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@param[in] InitialApicId Initial APIC ID of the target logical processor.
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@param[out] Package Returns the processor package ID.
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@param[out] Die Returns the processor die ID.
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@param[out] Tile Returns the processor tile ID.
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@param[out] Module Returns the processor module ID.
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@param[out] Core Returns the processor core ID.
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@param[out] Thread Returns the processor thread ID.
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**/
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VOID
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EFIAPI
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GetProcessorLocation2ByApicId (
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IN UINT32 InitialApicId,
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OUT UINT32 *Package OPTIONAL,
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OUT UINT32 *Die OPTIONAL,
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OUT UINT32 *Tile OPTIONAL,
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OUT UINT32 *Module OPTIONAL,
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OUT UINT32 *Core OPTIONAL,
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OUT UINT32 *Thread OPTIONAL
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);
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#endif
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