Commit Graph

12 Commits

Author SHA1 Message Date
Himanshu Sahdev 09245f4e54 BootloaderCore: Handle BIST failure in SecEntry (#311)
- Add BistVal in STAGE1A_ASM_HOB structure
- Use MM0 register to preserve the BIST value
- Push BistVal while setup HOB in stack
- Add check for CPU BIST failure and halt the system when failed

Signed-off-by: Himanshu Sahdev aka CunningLearner sahdev.himan@gmail.com
2019-09-06 09:10:41 -07:00
Maurice Ma 93b2e96d8e Add ContainerLib to support sub-region
This patch added a ContainerLib to support load and location a
component from a specified container. It copies the component
from flash to memory, authenticate it, and then decompress it if
required. It can also be used to support load component from flash
map in SBL stage2 or payload, such as payload or e-payload.

Signed-off-by: Maurice Ma <maurice.ma@intel.com>
2019-07-31 09:32:00 -07:00
Sai Talamudupula 1ca691339d [CFL] Restore regsiters on S3 resume
Restore the register information saved during the
normal boot, on S3 resume path for UEFI payload only.

Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
2019-07-26 10:04:13 -07:00
Guo Dong 5e10bd1e07 Update BSD license to BSD+Patent license
To align with EDK2, update file license
to use BSD+Patent license

Signed-off-by: Guo Dong <guo.dong@intel.com>
2019-06-13 10:46:49 -07:00
Guo Dong 9b24273090 Add ACPI_ENABLED()
Add ACPI_ENABLED() to align with MEASURED_BOOT_ENABLED().
Update MEASURED_BOOT_ENABLED() by checking PcdMeasuredBootEnabled
firstly.
Update PlatformFeaturesInit () in stage1b to fix potential inconsistent.
Update other code for changes above.

Signed-off-by: Guo Dong <guo.dong@intel.com>
2019-06-06 14:28:00 -07:00
Sai Talamudupula 5f09e82c10 Enhance SMMBASE_INFO communication structure
Match the strcture definition with payload

Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
2019-03-01 21:10:12 -08:00
Sai Talamudupula 14c3862005 Relocate SMM bases on S3 resume path
Smm bases for all the procs need to be relocated on the
S3 resume path (as payload is not run) for Windows boot.

Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
2019-02-26 11:23:29 -07:00
Maurice Ma a11fbf0538 Add multiple VBT table support
Current SBL can only support on VBT file. However, different board
might need different VBT table. It is better to have the capability
to embed multiple VBT table into the image.  This patch implemented
this feature and enabled it on QEMU. By default, it will take the
original behavior. if _MULTI_VBT_FILE in BoardConfig.py is specified,
multiple VBT files can be used.

If multiple VBT table support is required, list them as:
  {VbtImageId1 :VbtFileName1, VbtImageId2 : VbtFileName2, ...}
VbtImageId is ID to identify a VBT image. It is a UINT32 number to
  match the ImageId field in the VBT container.
VbtFileName is the VBT file name. It needs to be located under platform
  VbtBin folder.

Signed-off-by: Maurice Ma <maurice.ma@intel.com>
2019-02-13 17:15:33 -08:00
Guo Dong cd9edfdd8b Add Device table
Update core code to support device table.
Updated boot option to consume device table.
Update firmware update to consume device table.
Update shell command on boot option changes.
Add device table for APL and Qemu.
Remove unnecessary code.

Signed-off-by: Guo Dong <guo.dong@intel.com>
2018-11-12 09:38:59 -07:00
Maurice Ma dd3c729361 Rename KeyStore to HashStore to reduce confusion
Current code refers hash store as "key store". It is confusing
since there is no key stored in the image at all.  Instead, the
public key hash is stored.  The patch renames the KeyStore
to HashStore.

Signed-off-by: Maurice Ma <maurice.ma@intel.com>
2018-11-09 16:49:37 -08:00
Aiden Park e74b4e5ce5 Start DebugAgent from the beginning of Stage1B
Hardware Breakpoints must be used during CAR execution until
memory has been initiailzed for APL platform.

In order to use Hareware Breakpoints in UDK debugger, add
FlashRange in UDK config file and force to cover CAR area.
In SoftDebugger.ini of Windows UDK Debugger
Or In /etc/udkdebugger.conf of Linux UDK Debugger
  [Target System]
  FlashRange        = 0xFEF00000:0x1100000

Additionally,
  added Stage1BBase in STAGE1A_HOB
  fixed Stage1A module base report

Change-Id: I717f87bf141168de0b0987eb309fd4c5d48d3c14
Signed-off-by: Aiden Park <aiden.park@intel.com>
2018-10-16 14:47:13 -07:00
Maurice Ma c6999f497a Initial check-in for Slim Bootloader source 2018-09-13 16:11:07 -07:00