Currently, only absolute path is allowed in '-w' stitch_dir and '-s'
stitch_zip file. In addition, if stitch_dir is not absolute path, the
stitch tool looks for 'SBL_SOURCE' which does not exist in OS environment.
This patch allows the StitchIfwi.py tool to use relative path as well.
Signed-off-by: Aiden Park <aiden.park@intel.com>
Added a option in CFL StitchIfwi script to pass the TPM type to
be selected for Intel FIT tool stitching.
[TEST] = Run StitchIfwi.py with -tpm=dtpm for WHL
and verify use of dTPM.
Signed-off-by: Subash Lakkimsetti <subashx.lakkimsetti@intel.com>
BootPolicyManifest are required when a IFWI is
stitched with Intel BootGuard enabled. FlashMap maintains a pointer to
it so that SBL code can reach to them during execution.
This patch removes the check for its presence from IFWI images.
Test : Stitches Ok. Boots Ok.
Signed-off-by: Sachin Agrawal <sachin.agrawal@intel.com>
This patch is a follow-up patch of #380. If a platform disables HS400 mode,
silicon init code will configure eMMC in HS200. Other modes not in scope.
This will also fix#406.
Signed-off-by: Aiden Park <aiden.park@intel.com>
This patch allows a board to configure XDCI mode.
By default, keep XDCI mode as PCI mode which is default value in FSP.
The mode can be controlled by Config Data.
- Silicon Setting > Device Enable/Disable > Control 2 > Enable XDCI
If XDCI mode needs to be overrided, put new value in .dlt(delta) file.
- DEV_EN_CFG_DATA.DevEnControl2.XdciEnable | 0x0 (Disabled)
- DEV_EN_CFG_DATA.DevEnControl2.XdciEnable | 0x2 (ACPI mode)
It will fix#397 with the override value in a delta file.
Signed-off-by: Aiden Park <aiden.park@intel.com>
This patch adds IPC1 device to DSDT and exposes it to OS.
The behavior can be controlled by Config Data.
- Silicon Setting > Device Enable/Disable > Control 1 > IPC1 Enable/Disable
It also fixed#390.
Signed-off-by: Aiden Park <aiden.park@intel.com>
This patch changes the default behavior of gpio pin for payload
selection, currently user configured GPIO pin being high boots
to uefi payload, modified code will boot to OS loader when GPIO pin
is high.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
power button 4 second press will cause power button override
bit to set in PM1 status register, this bit is not cleared on
reset and is causing SMI storm during booting to OS.
Power button override bit if set is cleared now in stage1b and
this fixed the SMI storm issue.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
Current code set payload id depending on the gpio settings
and user selection from configuration data. When UEFI payload is
selected using GPIO or config data, payload id is being set to
UEFI irrespective of boot mode, which cause notification function
to get called, this locks the spi which inturn fails firmware update
Modified code to set payload id only in non-firmware update boot mode.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
This patch added csme wrapper driver for csme update library.
following functionality is added in this patch
1. Boardconfig PCD option ENABLE_CSME_UPDATE is added to
enable/disable csme update support
2. Boardconfig PCD option BUILD_CSME_UPDATE_DRIVER is added
to enable/disable building csme update driver
3. If BUILD_CSME_UPDATE_DRIVER is 1, user need to create
library that inludes csme update library
this newly created library will get linked to csme update
wrapper driver providing csme update driver
4. By default ENABLE_CSME_UPDATE is set to 0
5. Revision control for input and output data structure to
update driver is not implemented and will be avaiable
in further patches.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
UPX board has different memory configurations indicated by GPIO pins.
This patch added GPIO detections for these pins and set it as BomID.
It can be used to decide which SPD data to use later on.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch adjusted power related UPD settings to BIOS
UPD values are configurable through configuration data
After these changes, CPU maximum operating frequency
increased from 3.7GHZ to 4.2GHZ on WHL.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
This is to fit the size of the latest Debug UEFI Payload.
Increase the size from 0x00180000 to 0x00190000.
Signed-off-by: Aiden Park <aiden.park@intel.com>
StitchIfwi.py supports '-q' parameter to enable SPI QUAD mode.
However, it does not work as expected. When the script tries to
modify the XML file, it used 'yes' and 'no' as option values.
But it is case sensitive, and should use 'Yes' and 'No' instead.
This patch fixed this issue.
Test was done on LeafHill board and it enabled SPI QUAD mode
in IFWI after the fix. It fixed#370.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch allows APL and WHL(CFL) to use common header file for SPI
register access.
APL and CFL are using common SpiFlashLib and PchSpiLib, but Platform
code still refering to its own SPI registers header file.
- Remove duplicated header file
- Add common one to Silicon/CommonSocPkg
- Use SPI registers from common one in each Platform code
Signed-off-by: Aiden Park <aiden.park@intel.com>
mShellCommandCse is not defined in CoffeelakeBoardPkg so can't extern.
It is not either used in current context.
Signed-off-by: Himanshu Sahdev aka CunningLearner <sahdev.himan@gmail.com>
This patch switched to use SerialPortLib in BootloaderCommonPkg for
QEMU and CFL platforms. For APL platform, it can also use this common
library. However, it has an optimized SerialPortLib with FIFO enabled.
So for APL, it still uses its SOC specific library.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
The WHL(and CFL-R) has its own SpiFlashLib, but it's almost identical
to common SpiFlashLib except of silicon specific part.
Therefore, CoffeelakePkg will have its own PchSpiLib and re-use common
SpiFlashLib.
- Remove CoffeelakePkg SpiFlashLib and related files
- Use commmon SpiFlashLib
- Use CoffeelakePkg SpiFlashLib
Signed-off-by: Aiden Park <aiden.park@intel.com>
QEMU has its own SpiFlashLib and SpiFlashLib.h file.
But, the header file is identical to the one in Silicon/CommonSocPkg.
Therefore, remove QEMU's one and re-use the common header file from
Silicon/CommonSocPkg.
Signed-off-by: Aiden Park <aiden.park@intel.com>
Use common SpiFlashLib and PchSpiLib of Silicon/CommonSocPkg.
- No more use of SpiFlashLib from BootloaderCommonPkg
Signed-off-by: Aiden Park <aiden.park@intel.com>
On WHL after booting to Windows, SCI interrupt storm was seen due
to GPE event 111 (2-tier GPE event). This event needs to be handled
when RTD3 table is implemented. However, current code has _L6F
ASL code without RTD3 table. This causes the SCI event to be enabled
in Windows. Since there is no real handler to clear the SCI event,
SCI interrupt storm will occur. This patch commented out the _L6F ASL
method.
Tested this on WHL. The CPU utilization drop down from original 10%
to close to 0% for system interrupts.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Aiden Park
lsubash
Sachin Agrawal
Raghava Gudla
raghavag
Maurice Ma
Himanshu Sahdev aka CunningLearner