This patch added DMA memory type into memory allocation pool for payloads.
This DMA memory buffer with PcdDmaBufferSize is located at address
aligned at PcdDmaBufferAlignment after Payload reserved memory. Memory
type EfiRuntimeServicesData is used to indicate DMA memory type.
Stage1B calculates the DMA memory location using fixed PCDs so that
platform can set up DMA protection as early as possible after memory is
ready. In Stage1B or Stage2 platform code should use platform VTd
information to setup PMR to protect all low memory except for the DMA
buffer range. DMA memory will be added into memory pool at the entry
point of the payload. Before transfering to OS, the DMA memory protection
can be disabled, and the DMA memory pool can be reclaimed for OS usage.
Currently only boot media device will utilize the DMA buffer range for
block access operations. So it should only be required by payloads. GFX,
when enabled, will also use DMA. It will be targeted to the system stolen
memory which is not protected by PMR.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
FPDT size should be FIRMWARE_PERFORMANCE_TABLE. And updated
this logic to correct the size and adjust next ACPI table
starting address.
Signed-off-by: Guo Dong <guo.dong@intel.com>
This will allow OsLoader payload to boot to 64-bit kernel entry point.
If CPU supports 64-bit mode and a kernel image has 64-bit entry point,
OsLoader will switch to 64-bit long mode and jump to the 64-bit entry
point. Otherwise, continue to boot to 32-bit entry point.
- Ported necessary code from EDK2 VitualMemory.c in MdeModulePkg
- Moved PagingLib from BootloaderCorePkg to BootloaderCommonPkg
- Removed unused FlushCacheLine
- TBD: 64-bit IDT
Next step is to support 64-bit Payload.
- 32-bit compatible mode
- 64-bit CryptoLib
- etc.
Signed-off-by: Aiden Park <aiden.park@intel.com>
- Added GetHashToExtend to bootloader common API to
retrive digest to extend
- Hash calculations for stage component and config date updated
to use bootloader common API
- Added functionality to extend KeyHashManifest digest
Signed-off-by: Subash Lakkimsetti <subash.lakkimsetti@intel.com>
LoadComponentCallback is extended to perfom TPM extend
for firmware component stages. Component callback would be
invoked after authentication.
TpmExtendStageHash would extend hash based on hash validity.
TpmExtendConfigData is added to handle the Config data blob extend.
Signed-off-by: Subash Lakkimsetti <subash.lakkimsetti@intel.com>
This patch allows to setup Stage1 stack/data in any CAR range.
By default, the stack base offset is 0 from CarBase.
Signed-off-by: Aiden Park <aiden.park@intel.com>
This patch did some of the following clean up:
- Rename *_HOB to *_PARAM for Stage1A/Stage1B/Stage2.
This is to avoid confusion between real HOB and the parameter
data block passed through stages.
- Rename BistVal to CpuBist.
This is to make it more clear.
- Add BUF_INFO definition.
BUF_INFO will be used as a general structure.
- Remove CarBase/Top in Stage1B HOB
They are not used at all.
- Clean memory allocation in Stage1A
Restructured the buffer allocations for Stage1A global
data so that it is easier to read and maintain.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Hash and RSA signing parameters were hardcoded in
Crypto wrappers and secure boot libraries. This patch
address support for multiple hash and key sizes.
Signed-off-by: Subash Lakkimsetti <subashx.lakkimsetti@intel.com>
This will fully support PatchCheck.py.
- Remove all trailing whitespace
- Convert LF to CRLF by default
- Update EFI_D_* to DEBUG_*
- Re-enable CRLF check in PatchCheck.py
Signed-off-by: Aiden Park <aiden.park@intel.com>
Current SBL does not check the FSP Notify API return status. As a
result, if reset is requested, it is ignored by SBL. This patch
added FSP reset request check for FspMemoryInit, FspSiliconInit and
FspNotifyPhase.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch used the common API GetTimeStampFrequency() to get CPU
TSC frequency instead of the original GetCpuTscFreqency(). As part
of it, all SOC specific instances for GetCpuTscFreqency() were
removed.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
- Add BistVal in STAGE1A_ASM_HOB structure
- Use MM0 register to preserve the BIST value
- Push BistVal while setup HOB in stack
- Add check for CPU BIST failure and halt the system when failed
Signed-off-by: Himanshu Sahdev aka CunningLearner sahdev.himan@gmail.com
By design, BootloaderCommonPkg should not refer to
BootloaderCorePkg. Hence removed those references in
the .inf files in Common pkg.
Moving SmbiosInitLib to Core pkg as it is a core feature.
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
This patch added a ContainerLib to support load and location a
component from a specified container. It copies the component
from flash to memory, authenticate it, and then decompress it if
required. It can also be used to support load component from flash
map in SBL stage2 or payload, such as payload or e-payload.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
There are cases where temporary memory is required in stages. Since
MemoryAllocationLib instance for stages has no de-allocation function,
it needs special handling. This patch added temporary memory management
into standard MemoryAllocatoinLib interface.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Restore the register information saved during the
normal boot, on S3 resume path for UEFI payload only.
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
Add ACPI_ENABLED() to align with MEASURED_BOOT_ENABLED().
Update MEASURED_BOOT_ENABLED() by checking PcdMeasuredBootEnabled
firstly.
Update PlatformFeaturesInit () in stage1b to fix potential inconsistent.
Update other code for changes above.
Signed-off-by: Guo Dong <guo.dong@intel.com>
Some platform might need do some platform specific init
on all the threads. So add a MP hook using a PCD.
Np impact for the platform that doesn't need this hook.
This patch also enable InSMM bit for APL.
Signed-off-by: Guo Dong <guo.dong@intel.com>
Removing the HOB defined by SBL to use generic HOBs from EDK2.
Update GraphicsLib for above HOB change.
Update osloader and multibootLib for hob change.
update APL and Qemu platform for hob change.
Signed-off-by: Guo Dong <guo.dong@intel.com>
Smm bases for all the procs need to be relocated on the
S3 resume path (as payload is not run) for Windows boot.
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
This patch adds FPDT table into ACPI table, and updates all
the performance data for S3 path.
It also update basic boot performance data for reset end.
Other boot performance data could be updated by UEFI payload.
Signed-off-by: Guo Dong <guo.dong@intel.com>
Maurice Ma
Guo Dong
Aiden Park
Subash Lakkimsetti
Subash Lakkimsetti
Subash Lakkimsetti
Ravi Rangarajan
Himanshu Sahdev
Sai Talamudupula