The patch adds a feature to read Dts at boot. The feature
is analogous to UEFI BIOS:
Thermal Conf -> Platform Thermal Conf -> Boot DTS Read
Specifically, the feature reads Tjunctions of PCH and CPU
and stores them as Smbios Type-28 entries.
The patch also fixes AppendSmbiosType in SmbiosInitLib:
A newly added structure should inherit the Handle from
previous Type-127 (end-of-table) structure.
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
This patch fixes TSeg region full problem after multiple
warn reset. Each time of warm reset, except S3 resume, the
TSeg region should be clear.
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
This adds additional APIs to make Platform code use APIs to access
LoaderGlobalData instead of accessing variables directly.
- GetS3DataPtr()
- SetFeatureCfg()
- ClearFspHob()
- GetVerInfoPtr()
Signed-off-by: Aiden Park <aiden.park@intel.com>
Some platforms need TempRam Base & Size information to calculate
FspmArchUpd StackBase & Size at runtime.
The TempRam Base & Size info will be only valid until TempRamExit.
Signed-off-by: Aiden Park <aiden.park@intel.com>
This patch clears RTC Alarm when RTC is the S3 wake-up source.
Without clearing it, SMI# will be triggered once SMI_EN is set
by RestoreS3RegInfo, but no handler to clear it which results
in hang.
This patch also refactors RegRead/RegWrite in RestoreS3RegInfo
to avoid the misalingment of function pointers and coding
convention.
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
Currently it will return a valid SMMBASE_INFO if SMMBASE_INFO_COMM_ID
is found in SMM S3 resume memory. It will cause issue in S3 path if there
is no one fill correct data when MpInit uses it to rebase SMM.
This patch adds a check to SMMBASE_INFO to avoid this issue.
Signed-off-by: Guo Dong <guo.dong@intel.com>
This patch adds a platform hook function ability
in Pci Enum Lib to enable platform to perform
PCI Enum specific work-around routines.
Signed-off-by: Talamudupula <stalamudupula@gmail.com>
- fix __aullshr link error due to compiler intrinsics functions
for NOOPT build in Windows
- adjust Stage1A/TopSwap/OsLoader FD size for NOOPT target
- adjust Stage2 size for NOOPT target when DEBUG FSP is used
Signed-off-by: Vincent Chen <vincent.chen@intel.com>
This patch restructed MP init library so that more code can be
common between 32bit and 64bit. It is much easier to maintain the
code after the restructure.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch enables QEMU SMM TSEG programming in FSP. And it also
enables SBL QEMU SMM rebasing. It can be used to test many SMM
related flow.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
For appending Save/Restore structs in TSEG area,
bootloader should reserve space for TotalSize and
for certain structs, only header info should be
actually populated. Rest should be all Zeros.
Signed-off-by: Talamudupula <stalamudupula@gmail.com>
Current SBL SMM rebasing check is only performed when PcdSmmRebaseMode
is enabled. It does not cover the case to boot UEFI payload. This patch
enhaced the check to cover UEFI payload S3 path as well.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
When SMRR is enabled too early, it blocked TSEG access in Stage2.
And it caused S3 related issues. This patch delays the SMRR enabling
to be after PrePayloadLoading BoardInit().
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
For non UEFI payload, SBL will install dummy SMI handler for
security concern. For UEFI payload, SMM rebasing is expected
to be done itself. This patch enabled this feature for APL and
CFL platform.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
In normal UEFI payload case, the UEFI will handle SMM rebasing.
If SMM rebasing is handled by SBL, SBL will put a dummy SMI handler
at the new SMBASE to prevent SMM hang. Beyond SMM rebasing, it
is also required to program SMRR registers. This patch added this
support for core code. It also added TSEG PCD init for CFL.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This will disable all PCI bus master by default, and enable it only if
- the original bus master was enabled before PCI enumeration
- Or the device is PCI Bridge
Signed-off-by: Aiden Park <aiden.park@intel.com>
Current SBL release debug output has more than what is expected.
This patch reset some of the debug message to proper level to limit
debug message for release build.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch implemented a common method for platform to create ACPI
table dynamically. Platform can provide ACPI tempalte array through
PCD PcdAcpiTableTemplatePtr. If provided, ACPI core code will try to
call platform code to patch the table, and then install the table to
ACPI RSDT/XSDT.
It also added sample code implementation in QEMU to show case how to
do it from platform code.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
GCC x64 build requires stack to be aligned at 16 bytes. In MpInit
nasm file, SBL set the initial stack to be 16-byte aligned. However,
later on unbalanced push/pop breaks the 16-byte alignment. This
patch removed extra stack pop so that the stack will always stay at
the original initial value.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Current PCI Enum Lib scopes for only Apperture resources
for a PPB. But some OSes (like ESXi) expect BAR0 & BAR1
(Offset 0x10/0x14) to be allocated resources accordingly.
Otherwise, PPB enumeration doesnt happen correctly and
devices behind PPB are not registered at all.
This patch adds the functionality to assign valid resources
to BAR0(0x10) and BAR1(0x14) for a PPB also.
Signed-off-by: Talamudupula <stalamudupula@gmail.com>
This patch removed duplicated X2APIC enabling code. Instead, it
enables X2APIC in a common function. By doing so, the very first
waking up will be done in APIC mode. Afterwards, it will be using
X2APIC mode if enabled by PCD.
This patch also fixed an X2APIC ACPI MADT issue.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch added X2APIC support. It is to enable the case when
APIC ID is greater than 255. This patch only handle core wakeup
portion. Platform still needs to handle ACPI related changes for
X2APIC.
X2APIC lib is backward compatible with XAPIC lib. So there is no
need to use XAPIC lib anymore.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
The ApDataPtr->CProcedure was wrongly updated in previous patch.
This patch fixed it and CPU task name from CProcedure to TaskFunc
to avoid confusion.
Signed-off-by: Guo Dong <guo.dong@intel.com>
Stanley Chang
Aiden Park
Guo Dong
stalamudupula
Vincent Chen
James Gutbub
Maurice Ma