This patch fixes TSeg region full problem after multiple
warn reset. Each time of warm reset, except S3 resume, the
TSeg region should be clear.
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
This adds additional APIs to make Platform code use APIs to access
LoaderGlobalData instead of accessing variables directly.
- GetS3DataPtr()
- SetFeatureCfg()
- ClearFspHob()
- GetVerInfoPtr()
Signed-off-by: Aiden Park <aiden.park@intel.com>
Some platforms need TempRam Base & Size information to calculate
FspmArchUpd StackBase & Size at runtime.
The TempRam Base & Size info will be only valid until TempRamExit.
Signed-off-by: Aiden Park <aiden.park@intel.com>
Inconsistent and redundant header files are removed.
All projects going forward
- Use API declared in GpioLib.h
- Provide instance of GpioSiLib.h
- Use common defines in GpioConfig.h
[QEMU][APL][CFL][CML][CMLV]
- Follow above header model
- Have own instance of GpioLib
[EHL][TGL]
- Follow above header model
- Use common GpioLib instance
Signed-off-by: Talamudupula <stalamudupula@gmail.com>
This patch adds a platform hook function ability
in Pci Enum Lib to enable platform to perform
PCI Enum specific work-around routines.
Signed-off-by: Talamudupula <stalamudupula@gmail.com>
For appending Save/Restore structs in TSEG area,
bootloader should reserve space for TotalSize and
for certain structs, only header info should be
actually populated. Rest should be all Zeros.
Signed-off-by: Talamudupula <stalamudupula@gmail.com>
The ApDataPtr->CProcedure was wrongly updated in previous patch.
This patch fixed it and CPU task name from CProcedure to TaskFunc
to avoid confusion.
Signed-off-by: Guo Dong <guo.dong@intel.com>
Point TGL project to use common GpioLib and fix build errors.
GpioPlatformLib instance for TGL platform is also provided
as a reference for other platforms. Also remove TGL specific
Gpio Library related files.
Usage:
To configure Gpio pins provided by GPIO CFG DATA:
ConfigureGpio(Gpio_Cfg_Data_Tag, 0, NULL);
To configure Gpio pins provided by GPIO_INIT_CONFIG array:
ConfigureGpio(0, Num_entries, Ptr_to_Array);
Signed-off-by: Talamudupula <stalamudupula@gmail.com>
This patch adds a common GpioLib that all platforms
can link to. Common GpioLib requires platforms to
implement the GpioInfoLib to provide platform-specific
information like GroupInfo etc.
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
- Default SMBIOS Table initialized when SMBIOS is enabled.
- If required, Every Platform can override platform specific information.
- Enable SMBIOS in Qemu platform.
- Update Memory allocation for SmbiosStringsPtr for 32 entries.
Signed-off-by: Sm NARAYANAN <s.m.narayanan@intel.com>
This patch will generate a SW smi on S3 resume path when using
UEFI payload. Handler for this Sw smi in UEFI payload will
program SMRR base and mask for BSP and all AP's.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
Current container library cannot be used before memory is initialized
because the structure will only be initialized after memory. This
patch moved the initialization into Stage1A so that the library can be
used much earlier. The containers registered before memory will be
migrated into memory automatically post memory initialization. In this
way it avoids duplicated header authentication.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This will fix stage transition failures for X64 targets built with gcc
which is caused by mis-matched EFIAPI calling convention.
- Add EFIAPI to STAGE_ENTRY interface for Stage1A -> Stage1B
- Add EFIAPI to PAYLOAD_ENTRY interface for Stage2->OsLoader Payload
- Remove unused KERNEL_ENTRY interface
Signed-off-by: Aiden Park <aiden.park@intel.com>
In certain condition, the FspTempRamExit() API will be executed from
CAR. If so, the thunk call itself cannot be in CAR otherwise the
call will hang immediately after the CAR teardown. To resolve it,
the thunk call needs to be copied over to memory before calling the
FspTempRamExit() API. This patch implemented this.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
* [QEMU] Enable Stage1A boot in X64 mode
This patch added necessary changes to enable QEMU boot through
Stage1A in SBL X64 build.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
* [QEMU] Enable QEMU Linux boot in X64 mode
This patch enabled SBL X64 boot for Linux. At this moment, since
FSP is still in 32 bit mode, it is required to thunk back into
32 bit mode to call FSP APIs.
It fixed#622.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Due to missing normal function implementations in some x64 code, GCC
optimized many code off from the final image which caused synbol
patching issue later on. This patch fixed this.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
There are lots of common code in Stage1A/1B/2, so it makes sense
to put those into a StageLib so that the same code can be reused.
As part of it, PagingLib is also restructured to align with Stage
mapping/remapping. It will consider both X64 mode and IA32 mode.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch allows both 32/64-bit addressing properly.
- Pointer type cast with UINTN
- Add missing EFIAPI for APIs
Signed-off-by: Aiden Park <aiden.park@intel.com>
This patch opitmized GDT loading in different stages. The old code
put GDT in code segment so it needs to be relocated every time when
code relocation/remapping occurs. By putting GDT into heap, it avoids
the GDT reloading. It only needs to be done twice, PreMem and PostMem.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch added DMA memory type into memory allocation pool for payloads.
This DMA memory buffer with PcdDmaBufferSize is located at address
aligned at PcdDmaBufferAlignment after Payload reserved memory. Memory
type EfiRuntimeServicesData is used to indicate DMA memory type.
Stage1B calculates the DMA memory location using fixed PCDs so that
platform can set up DMA protection as early as possible after memory is
ready. In Stage1B or Stage2 platform code should use platform VTd
information to setup PMR to protect all low memory except for the DMA
buffer range. DMA memory will be added into memory pool at the entry
point of the payload. Before transfering to OS, the DMA memory protection
can be disabled, and the DMA memory pool can be reclaimed for OS usage.
Currently only boot media device will utilize the DMA buffer range for
block access operations. So it should only be required by payloads. GFX,
when enabled, will also use DMA. It will be targeted to the system stolen
memory which is not protected by PMR.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Stanley Chang
Aiden Park
Talamudupula
Guo Dong
Maurice Ma
Sai Talamudupula
Singh Nitin G
Sm NARAYANAN
Raghava Gudla