This commit adds support for PCIe resizable BARsupport.
The feature can be enabled by setting PcdResizableBarSupport
for the board build script and its disabled by default.
Signed-off-by: pastorcx <mariano-paulx.pastorcici@intel.com>
Adding new Board Config item REMAP_STAGE1B to control remapping Stage1B
into permanent memory after FSP-M. Decouple this from ENABLE_FAST_BOOT
and STAGE1B_XIP. This makes it simpler to enable this remap when the
slight performance boost may be needed, and leave it disabled by default.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
1) Some FSP 2.4 implementations are non-conforming and use FSPM_ARCH_UPD
instead of FSPM_ARCH2_UPD as indicated by the specification. Logic is
changed to check FSPM UPD header revision for structure version instead
of FSP spec revision.
2) MultiPhase FSP PhaseIndex is one-based so loop comparisons need to take
this into account. Side effect is that the last phase may be missed. No
current platform FSP is utilizing this.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
This will increase time of Board PostMemoryInit hook and TempRamExit,
but improve the performance of PostTempRamExit hook, PreSiliconInit hook
and FSP-S.
In total, the boot time can be reduced by ~20ms.
Signed-off-by: Yi Li <yi1.li@intel.com>
Registering logical root bridges with no devices can cause unexpected
behavior for platforms that use _PCI_ENUM_BUS_SCAN_TYPE = "range", since
all empty buses in the range will be compared against the resource
allocation table entries.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
Not all root bridges have a physical device at dev 0 func 0 of the root
bus, and this requirement prevents some platforms from being fully scanned.
From this point, PciEnumerationLib doesn't access the root bridge
configuration space at all, so this is an unnecessary check.
Instead, root bus scanning will continue without dev 0 func 0 present. If
no devices are found on the root bus, scanning will continue to the next
root bridge.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
The SBL logo is verified as part of Stage2 verification, so untrusted
logos won't be parsed, but it's still good to prevent dereferencing BMP
header pointers that may fall outside of BMP file.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
Update the FPDT header length to include the length
of boot records. This way we could easily get all the
boot records from dumped ACPI FPDT table.
Signed-off-by: Guo Dong <guo.dong@intel.com>
Since # of PROCESSOR_LOCAL_APICs are
Madt Local Apic # is 1.
Madt X2 Local Apic # is 9.
Need to update # of structure type of X2Apic.
Signed-off-by: cshur <cs.hur@intel.com>
In current code, BoardNotifyPhase() would update FPDT SBL performance
table in S3 path. It could cause S3 issue since PcdAcpiTablesRsdp is
not updated.
Move the FPDT related code to AcpiFpdt.c
Update FPDT SBL performance table in stage2 so that this table
could be updated for all payloads.
Signed-off-by: Guo Dong <guo.dong@intel.com>
- Add a null check for Rsdp pointer before accessing it
- Initialize ResetVectorTime, Time to some value before using it
- Add debug print for success / failure
Signed-off-by: Atharva Lele <atharva.lele@intel.com>
FSP 2.4 adds a requirement for Bootloader to respond to FSP Variable
requests in a way that is similar to UEFI variable services. This
implementation adds support for using the updated SBL VariableLib so that
the FspVariableServicesLib wrapper is no longer needed.
Additionally, support for Multi-Phase mem and SI init is added. FSP 2.4
introduces the mandatory MultiPhaseMemInit call, and makes the
MultiPhaseSiInit call mandatory where it was previously optional.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
Adds SBL boot performance data (Stage1 time, Stage 2 time, OsLoader time)
to the FPDT with type 0x3000 (Reserved for platform firmware Vendor usage)
Other fixes:
- Move logging of measure point 40F0 inside the condition for measured boot
- Add missing call to log measure point 40E0 used to log kernel setup print
time
Signed-off-by: Atharva Lele <atharva.lele@intel.com>
Re-scanning PCI devices to find NVME controllers was adding an additional
~20ms to the end of Stage 2. Moving this to the existing PCI scan that
is part of PCI enumeration saves this time. However, this
EfiPciBeforeResourceCollection phase was not actually getting called and
needed to be added.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
Silicon Reset Lib needs to know the FSP reset request status since some
FSPs will utilize Reset values besides warm/cold.
Added support for ADl/RPL global reset request from FSP.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
When SG02 is failing on both partitions, a shutdown is supposed
to occur after trying to boot from each partition 3 times. However,
it was noticed that this was not occurring as the shutdown function
was left empty. This caused dead loops and further ACM active timer
expirations.
This change resolves this issue by moving the TCO timer check and start
until after the ACM active timer has been stopped. This change also converts
the shutdown to a CPU halt for further clarity.
Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
There is no way to recover from failure in the following scenarios:
1) Both BP0 and BP1 are corrupted
2) The configured PLD is not found
A CPU halt does not prevent the TCO timer from rebooting.
This change makes it so that the SUT shuts down whenever a
unrecoverable failure occurs, so that it does not incorrectly enter
the recovert loop.
Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
It was discovered that the ACM active timer monitors
boot progress across all of SG1A and the beginning of
SG1B (through FSP-M), flipping the TS if it times out.
This change makes it so that the 2 timers have less
overlap.
This change also consolidates the set and start TCO timer
APIs as well as renames the TCO status check API.
Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
Code are shared for AlderLake and RaptorLake.
Just update the SMBIOS strings to reflect it.
Signed-off-by: Guo Dong <guo.dong@intel.com>
Signed-off-by: Guo Dong <guo.dong@intel.com>
Pastorcici, Mariano-paulX
Bejean Mosher
bejeanmo
Yi Li
Chirag Vijay Kolhe
Guo Dong
cshur
Sachin Kamat
Kevin Tsai
Guo Dong
Atharva Lele
koktong-ong
Sean McGinn