library
Migrates FW resiliency APIs of Stage1B.c to
FirmwareResiliencyLib
Migrates FW update status types from FirmwareUpdateLib.h and
BootloaderCommonLib.h to FirmwareUpdateStatus.h
Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
- Increase PlatformMemorySize to get rid of FSP error caused
during Tcc SRAM init.
- Sort the CPUs in ascending order for Tcc validation purpose.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
Different use case might want to have a different CPU order.
e.g. P-core first or E-core first.
This patch adds an option to help user sort CPU.
platform could add "self.CPU_SORT_METHOD = value" to
BoardConfig.py to override the default value.
Signed-off-by: Guo Dong <guo.dong@intel.com>
Current SBL PCI enumeration does not allocate resource for PCI ROM
bar because SBL does not deal with option ROM at all. However, the
Linux kernel might expect the ROM bar resource to be allocated.
This patch introduces a static build configuration to allow support
PCI resource allocation for PCI ROM bar.
To enable this feature, please add following into the project
BoardConfig.py file:
self._PCI_ENUM_FLAG_ALLOC_ROM_BAR = 1
By default, it will be disabled to keep the same behavior as before.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
EDK2 stable tag 202111 changed some field name in SMBIOS structure.
This patch matched the changes to fix the build issue for SBL. It
also added new library class in DSC.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
When we die due to a fatal exception, we get a debug message that
looks like this:
Exception #6 from 0x0010:0x000728E9 !!!
This message by itself is not incredibly useful for figuring out
which code caused the exception.
This patch borrows an idea from the Linux kernel, and extends the
exception information with a dump of the opcode bytes around the
instruction pointer, which means that the exception debug message
will now look like this:
Exception #6 from 0x0010:0x000728E9 !!!
000728C9: 07 00 6A 40 E8 E0 E8 FF-FF 83 C4 0C 68 00 00 07 [...]
000728D9: 00 68 DA 3A 07 00 6A 40-E8 CC E8 FF FF 83 C4 10 [...]
000728E9: 0F 0B E8 8E F2 FF FF 8D-55 98 80 78 0E 01 8D 45 [...]
000728F9: 94 75 06 52 50 6A 01 EB-04 52 50 6A 00 68 53 47 [...]
Tested by inserting a UD2 instruction into Stage1A and verifying on
qemu ia32 and on qemu x64 that the right information is printed.
Signed-off-by: Lennert Buytenhek <buytenh@arista.com>
This patch does the following updates to SmBiosInitLib:
1. Provide AddSmbiosType() to add a SmBios Type header.
2. Provide AddSmbiosString() to append strings to Type header.
3. Move Finalize() to after 'PrePayloadLoading' board init phase.
All Smbios related calls need to be done before this.
4. Modified TGL project to adjust to these changes.
Signed-off-by: Sai T <sai.kiran.talamudupula@intel.com>
Convert the line endings stored for all text files in the repository to
LF. The majority previously used DOS-style CRLF line endings. Add a
.gitattributes file to enforce this and treat certain extensions as
never being text files.
Update PatchCheck.py to insist on LF line endings rather than CRLF.
However, its other checks fail on this commit due to lots of
pre-existing complaints that it only notices because the line endings
have changed.
Silicon/QemuSocPkg/FspBin/Patches/0001-Build-QEMU-FSP-2.0-binaries.patch
needs to be treated as binary since it contains a mixture of line
endings.
This change has implications depending on the client platform you are
using the repository from:
* Windows
The usual configuration for Git on Windows means that text files will
be checked out to the work tree with DOS-style CRLF line endings. If
that's not the case then you can configure Git to do so for the entire
machine with:
git config --global core.autocrlf true
or for just the repository with:
git config core.autocrlf true
Line endings will be normalised to LF when they are committed to the
repository. If you commit a text file with only LF line endings then it
will be converted to CRLF line endings in your work tree.
* Linux, MacOS and other Unices
The usual configuration for Git on such platforms is to check files out
of the repository with LF line endings. This is probably the right thing
for you. In the unlikely even that you are using Git on Unix but editing
or compiling on Windows for some reason then you may need to tweak your
configuration to force the use of CRLF line endings as described above.
* General
For more information see
https://docs.github.com/en/get-started/getting-started-with-git/configuring-git-to-handle-line-endings .
Fixes: https://github.com/slimbootloader/slimbootloader/issues/1400
Signed-off-by: Mike Crowe <mac@mcrowe.com>
SBL might change MTRR to enable framebuffer cache. Current code
only handles BSP MTRR programming, and it is necessary to sync
up the MTRR programming for all APs as well. This patch added
a function to sync up MTRRs for all APs.
Please note, this MTRR sync up is a simplified version for SBL
case since SBL will only add new MTRRs for GFX framebuffer.
To do a full generic MTRRs sync up, it is required to flush cache,
reload TLB, etc. And it will come with some performance impacts.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
UEFI payload built from open sourced EDK2 supports SMM variable now.
So build the required HOBs to work with EDK2.
This patch just changed the common SBL code, so there is no platform
change required.
This patch also added a PCD PcdBuildSmmHobs for old SMM HOBs and new
SMM HOBs. Late old SMM HOBs might be dropped.
Signed-off-by: Guo Dong <guo.dong@intel.com>
This patch moved SBL core private data strctures and definitions
into a private header file so that other packages cannot refer
to the private structures.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch added API to Get/SetSocSku. In current code, SBL always
read the PCI register to determine the SKU. It is not efficient.
Since it is used a lot, it is better to have software API to get
this info through a software only method.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
In order to report memory size info in SMBIOS table, it is required
to know the full system memory. However, all info can only be passed
through FSP HOB, and it cannot easily identify the top of low/high
memory. The patch added core API GetMemoryInfo/SetMemoryInfo so that
platform can provide required memory info for core. By default, it
uses FSP hobs to guess these info. But platform can update it with
more accurate info during PostMemoryInit phase.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch reworked the previous reverted commit. The UEFI payload
debug version assertion was resolved. Checked in Windows, the SMBIOS
info looks good.
Current UEFI payload showed 0 KB RAM size in setup screen because
of missing SMBIOS memory type information. This patch added SMBIOS
type 19 to provide memory array mapped address information. With
this change, UEFI setup screen can show correct memory size.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch added PcdAcpiProcessorIdBase to allow platform to
customize the processor ID start base within MADT APIC entry.
Current EHL and TGL declared PR00 processor object in ACPI
with unique ID value 0, but other projects used vlaue 1
instead. This patch will help fix this issue.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This records the maximum usage of heap at runtime. The Stage1/2 heap
sometimes reaches OUT OF RESOURCE even if it looks there is enough
usable space in the heap. This is because AllocateTemporaryMemory()
sometime exceeds the heap boundary. ex) IppCryptoLib
This would help identify proper heap size required in each stages.
Signed-off-by: Aiden Park <aiden.park@intel.com>
This reverts commit b87d67c1fc.
In the testing, it caused debug UEFI payload assertion issue.
Roll it back for now.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Current UEFI payload showed 0 KB RAM size in setup screen because
of missing SMBIOS memory type information. This patch added SMBIOS
type 19 to provide memory array mapped address information. With
this change, UEFI setup screen can show correct memory size.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
On TGL platform, when enable SR_IOV for PCI enumeration, system
hung due to insufficient PCI resource. GFX VF needs lots of MMIO
resource and it cannot be satisfied by SBL in 32 bit mode.
To address this issue, this patch extends the bus 0 downgrade
policy to further allow downgrading PCI bus 0 devices except for
GFX. Now the DowngradeBus0 policy has following values:
0: Do not downgrade PCI devices on bus 0
1: Downgrade all PCI devices on bus 0
2: Downgrade all PCI devices on bus 0 but GFX
3: Reserved
By default, it has the same behavior as before. If platform needs
to download bus 0 devices but GFX, the new value 2 can be used.
This has been tested on TGL, and it worked as expected.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch enabled ELF UEFI Universal Payload boot for SBL. It was
tested with EDK2 commit 22873f58c40c496d59a0553bee1c720192ac35c9.
To build UEFI Universal Payload, please run script from EDK2 repo:
edksetup.bat
python UefiPayloadPkg\UniversalPayloadBuild.py -b DEBUG -t VS2019
The generated payload binary will be located at:
Build\UefiPayloadPkgX64\UniversalPayload.elf
This patch was tested on QEMU, and it worked as expected.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
