Added fips_selftest run before any crypto use in Stage1A.
updated IppCrypto to 1.0.1 version
Signed-off-by: Antara Borwankar <antara.borwankar@intel.com>
IAS boot image format is deprecated; it is recommended to use container
boot image.
- Removed references,files related to IAS image.
- Replaced IAS image boot options with container type image.
Signed-off-by: Chirag Vijay Kolhe <chirag.vijay.kolhe@intel.com>
FSP 2.4 introduces the possibility of FSP built for x64 architecture.
This adds support for x64 FSP calling conventions based on the header x64
support attribute. Support for x64 FSP-T requires entering long mode
prior to FSP-T execution.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
Some silicon requires longer than provided for all APs to enter the wakeup
routine. This change makes this platform configurable. The default wait
time is none and can be increased for platforms with higher core count Si.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
When multiple versions of Visual Studio (VS) were installed, the BaseTools
would be built with the latest version, regardless of user preference
(i.e., specified by the "-t" option). This behavior was incorrect for users
needing to build with a specific VS. This commit addresses the issue by aligning
the BaseTools to build with the user-specified version of VS.
Test steps:
0. Two versions of VS are installed: VS2017 and VS2022
1. Default build: python BuildLoader.py build tgl
2. Build with specific version: python BuildLoader.py build tgl -t vs2022
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
Adding new Board Config item REMAP_STAGE1B to control remapping Stage1B
into permanent memory after FSP-M. Decouple this from ENABLE_FAST_BOOT
and STAGE1B_XIP. This makes it simpler to enable this remap when the
slight performance boost may be needed, and leave it disabled by default.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
The SBL logo is verified as part of Stage2 verification, so untrusted
logos won't be parsed, but it's still good to prevent dereferencing BMP
header pointers that may fall outside of BMP file.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
FIT4 Entry is needed for PCH-less Server platforms to execute CBnT
and/or PFR. By default, FIT4 Entry will not come into the scenario.
It needs to enable from BoardConfig.py for specific platforms.
Signed-off-by: Biswas Arghya <arghya.biswas@intel.com>
ADL groups GPIO pins into different sets for different PCH series.
The current CfgData uses ADLS's GPIO group sets as the base, and
overwrites the GrpIdx fields via DLT files for other PCH series.
This results in two issues:
1. "CfgDataTool.py export" command failed to extract DLT files
from SBL image, since it cannot identify the proper group
index in CfgDataExt.bin from the base table in CfgDataInt.bin
2. When using ConfigEditor.py to configure the PadGroup field of
GPIO Payload Selection, it will map to a wrong group index.
This patch separates CfgDataDef.yaml for each of PCH series
- add _CFGDATA_DEF_FILE in BoardConfig.py
- add board extension yaml files for Adln, Adlp, Adls
* CfgDataDef*.yaml
* CfgData_Gpio_*.yaml
* CfgData_PayloadSelection_*.yaml
- assign an invalid/unique GrpIdx for the unused GPIO group
* e.g. 1F, 1E, ..
- adjust GrpIdx of CfgDataExt_Upx12.dlt based on Adlp
- revise the payload selection information in DLT files
This patch also fixes the issue:
- When ConfigEditor opens CfgDataDef.yaml more than once, the
config changes will not be caught by "Save Config Changes to
Delta File"
It is because the "info" argument of build_cfg_list() in
GenCfgData.py will retain its value in the lifetime of
ConfigEditor, and the offset will overflow. So need to reset
the offset for a fresh load_yaml().
Signed-off-by: Vincent Chen <vincent.chen@intel.com>
1.Build script will not copy FSP, VBT and Microcode bin files from repository
if it finds these files existing in taget folders.
Above step keeps them from unintentional update in series of build process.
Adding a board name to clean command helps to get latest binaries from repository
in next build.
2.Ignore empty board name from loading BoardConfig*.py
Signed-off-by: Kevin Tsai <kevin.tsai@intel.com>
platforms
Update Build scripts to take a different file path and Name
for
-- microcode_inf_file
-- fsp_inf_file
Signed-off-by: Barnes <kimberly.d.barnes@intel.com>
platforms
Update Build scripts to take a different file path and Name
for
-- microcode_inf_file
-- fsp_inf_file
Signed-off-by: Barnes <kimberly.d.barnes@intel.com>
Currently, FlashMap.txt is generated *after* the output files are copied.
This results in FlashMap.txt being missing from the output folder on a
clean build. On subsequent rebuilds, the FlashMap.txt is from the previous
build so any layout changes are not reflected.
Signed-off-by: Atharva Lele <atharva.lele@intel.com>
* OsLoader: set default status to EFI_UNSUPPORTED when parsing a boot image
This was set to EFI_SUCCESS which resulted in ParseBootImages() returning
EFI_SUCCESS even if the boot image was not a container or a component.
Thus, the boot would continue and fail at a later stage due to the
LoadedImage structure not being populated correctly.
Setting it to EFI_UNSUPPORTED will result in ParseBootImages() returning
EFI_UNSUPPORTED if a non-supported boot image is provided and OsLoader
will attempt to boot the next entry in the boot options list.
Signed-off-by: Atharva Lele <atharva.lele@intel.com>
* Remove PcdContainerBootEnabled PCD
SBL requires boot images to be packaged as a container or a component
Signed-off-by: Atharva Lele <atharva.lele@intel.com>
---------
Signed-off-by: Atharva Lele <atharva.lele@intel.com>
The FIT allows for some empty uCode slots to be defined
in anticipation of future uCode updates. This change adds
as many empty slots as possible after the non-empty slots
in the uCode region.
Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
During the build process, SG1A is built
for BP0 and a copy is made for BP1. Then,
the parameters of the BP1 SG1A are adjusted
to reflect that it is in BP1. One of the
parameters that gets adjusted during this
process is the uCode base. It was noticed
that this uCode base does not get updated
at all for platforms using FSP spec 2.2, but
another parameter gets updated instead.
Specifically, the error is in the FSP-T UPD
struct. The offset of the uCode base in
the FSP-T UPD struct is 0x40 for platforms using
FSP spec 2.2. However, the offset that actually
gets updated for platforms using FSP spec 2.2 is
0x20. This change corrects this offset for the
relevant platforms.
Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
