Currently SBL supports SMM REBASE based on configuration.
1) When payload doesn't support SMM, SBL need enable SMM rebase.
So SBL will rebase SMM to SMRAM and set SMRR to prevent SMRAM
access out of SMM and prevent payload SMM driver dispatch.
2) When payload support SMM, SBL need disable SMM rebase.
In this case SBL do nothing for SMM. Payload will do SMM
rebase.
In new UEFI payload (after stable branch 202311), SMM relocation
was removed CPU SMM driver. To work with new UEFI payload, SMM
relocation is expected in SBL, but SMRR should not be set so that
SMM drivers in UEFI payload could be dispatched into SMRAM.
This patch adds a new SMM rebase configuration that it rebase SMM
but it doesn't set SMRR.
Currently SBL supports rebase AUTO setting based on payload. This
patch also add auto support.
Signed-off-by: Guo Dong <guo.dong@intel.com>
Some silicon requires longer than provided for all APs to enter the wakeup
routine. This change makes this platform configurable. The default wait
time is none and can be increased for platforms with higher core count Si.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
- Increase PlatformMemorySize to get rid of FSP error caused
during Tcc SRAM init.
- Sort the CPUs in ascending order for Tcc validation purpose.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
Different use case might want to have a different CPU order.
e.g. P-core first or E-core first.
This patch adds an option to help user sort CPU.
platform could add "self.CPU_SORT_METHOD = value" to
BoardConfig.py to override the default value.
Signed-off-by: Guo Dong <guo.dong@intel.com>
Convert the line endings stored for all text files in the repository to
LF. The majority previously used DOS-style CRLF line endings. Add a
.gitattributes file to enforce this and treat certain extensions as
never being text files.
Update PatchCheck.py to insist on LF line endings rather than CRLF.
However, its other checks fail on this commit due to lots of
pre-existing complaints that it only notices because the line endings
have changed.
Silicon/QemuSocPkg/FspBin/Patches/0001-Build-QEMU-FSP-2.0-binaries.patch
needs to be treated as binary since it contains a mixture of line
endings.
This change has implications depending on the client platform you are
using the repository from:
* Windows
The usual configuration for Git on Windows means that text files will
be checked out to the work tree with DOS-style CRLF line endings. If
that's not the case then you can configure Git to do so for the entire
machine with:
git config --global core.autocrlf true
or for just the repository with:
git config core.autocrlf true
Line endings will be normalised to LF when they are committed to the
repository. If you commit a text file with only LF line endings then it
will be converted to CRLF line endings in your work tree.
* Linux, MacOS and other Unices
The usual configuration for Git on such platforms is to check files out
of the repository with LF line endings. This is probably the right thing
for you. In the unlikely even that you are using Git on Unix but editing
or compiling on Windows for some reason then you may need to tweak your
configuration to force the use of CRLF line endings as described above.
* General
For more information see
https://docs.github.com/en/get-started/getting-started-with-git/configuring-git-to-handle-line-endings .
Fixes: https://github.com/slimbootloader/slimbootloader/issues/1400
Signed-off-by: Mike Crowe <mac@mcrowe.com>
SBL might change MTRR to enable framebuffer cache. Current code
only handles BSP MTRR programming, and it is necessary to sync
up the MTRR programming for all APs as well. This patch added
a function to sync up MTRRs for all APs.
Please note, this MTRR sync up is a simplified version for SBL
case since SBL will only add new MTRRs for GFX framebuffer.
To do a full generic MTRRs sync up, it is required to flush cache,
reload TLB, etc. And it will come with some performance impacts.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
UEFI payload built from open sourced EDK2 supports SMM variable now.
So build the required HOBs to work with EDK2.
This patch just changed the common SBL code, so there is no platform
change required.
This patch also added a PCD PcdBuildSmmHobs for old SMM HOBs and new
SMM HOBs. Late old SMM HOBs might be dropped.
Signed-off-by: Guo Dong <guo.dong@intel.com>
This patch restructed MP init library so that more code can be
common between 32bit and 64bit. It is much easier to maintain the
code after the restructure.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch enables QEMU SMM TSEG programming in FSP. And it also
enables SBL QEMU SMM rebasing. It can be used to test many SMM
related flow.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Current SBL SMM rebasing check is only performed when PcdSmmRebaseMode
is enabled. It does not cover the case to boot UEFI payload. This patch
enhaced the check to cover UEFI payload S3 path as well.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
When SMRR is enabled too early, it blocked TSEG access in Stage2.
And it caused S3 related issues. This patch delays the SMRR enabling
to be after PrePayloadLoading BoardInit().
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
For non UEFI payload, SBL will install dummy SMI handler for
security concern. For UEFI payload, SMM rebasing is expected
to be done itself. This patch enabled this feature for APL and
CFL platform.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
In normal UEFI payload case, the UEFI will handle SMM rebasing.
If SMM rebasing is handled by SBL, SBL will put a dummy SMI handler
at the new SMBASE to prevent SMM hang. Beyond SMM rebasing, it
is also required to program SMRR registers. This patch added this
support for core code. It also added TSEG PCD init for CFL.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
GCC x64 build requires stack to be aligned at 16 bytes. In MpInit
nasm file, SBL set the initial stack to be 16-byte aligned. However,
later on unbalanced push/pop breaks the 16-byte alignment. This
patch removed extra stack pop so that the stack will always stay at
the original initial value.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch removed duplicated X2APIC enabling code. Instead, it
enables X2APIC in a common function. By doing so, the very first
waking up will be done in APIC mode. Afterwards, it will be using
X2APIC mode if enabled by PCD.
This patch also fixed an X2APIC ACPI MADT issue.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch added X2APIC support. It is to enable the case when
APIC ID is greater than 255. This patch only handle core wakeup
portion. Platform still needs to handle ACPI related changes for
X2APIC.
X2APIC lib is backward compatible with XAPIC lib. So there is no
need to use XAPIC lib anymore.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
The ApDataPtr->CProcedure was wrongly updated in previous patch.
This patch fixed it and CPU task name from CProcedure to TaskFunc
to avoid confusion.
Signed-off-by: Guo Dong <guo.dong@intel.com>
There is request to utilize MP in OsLoader. To support it, it is
desired to delay MP init done signal to the end of the OsLoader.
This patch moved the MP init done signal into board ReadyToBoot
notification so that MP is still alive in OsLoader phase.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This will support S3 resume path on X64 thru 16-bit waking vector.
- Port WakeUp code from EDKII
- Remove duplicated calls of FindS3Info from CpuInit
- Verified with Yocto on a WHL board
- TBD: 64-bit waking vector with supported OS
Signed-off-by: Aiden Park <aiden.park@intel.com>
This will fix MpInit failure on X64 build.
The ApFunc() gets invalid parameters due to mismatched calling convention.
- Add EFIAPI to match calling convention
This can be verified with '-smp' option on QEMU target.
qemu-system-x86_64
-machine q35 -m 256 -nographic -serial mon:stdio
-pflash Outputs/qemu/SlimBootloader.bin
-smp 255
Signed-off-by: Aiden Park <aiden.park@intel.com>
